ARM1136JF-S and ARM1136J-S Technical Reference Manual: 6.10. Fault status and address

6.10. Fault status and address

The encodings for the Fault Status Register are shown in Table 6.13.

Table 6.13. Fault Status Register encoding

Priority	Sources		FSR[10,3:0]	Domain	FAR
Highest	Alignment		b00001	Invalid	Valid
	Cache maintenance^[a] operation fault		b00100	Invalid	Valid
	External abort on translation	First-level	b01100	Invalid	Valid
		Second-level	b01110	Valid	Valid
	Translation	Section	b00101	Invalid	Valid
		Page	b00111	Valid	Valid
	Access Flag fault^[b]	Section	b00011^[c]	Valid	Valid
		Page	b00110^[c]	Valid	Valid
	Domain	Section	b01001	Valid	Valid
		Page	b01011	Valid	Valid
	Permission	Section	b01101	Valid	Valid
		Page	b01111	Valid	Valid
	Precise External Abort		b01000	Valid	Valid
	Imprecise External Abort		b10110	Invalid	Invalid
Lowest	Debug event		b00010	Valid	Invalid
^[a]These aborts cannot be signaled with the IFSR because they do not occur on the instruction side. ^[b]These aborts can only occur if enabled by setting the AFE bit, bit[29], in the CP15 Control Register, see c1, Control Register. In addition, the AFE bit is only considered if the XP bit, bit[23], in the CP15 control register is set (ARMv6 mode). Access Flag Faults are only defined from the rev1 (r1p0) release of the ARM1136JF-S processor, and these FSR encodings are reserved in rev0 RTL releases. ^[c]Because of the limited encoding space for FSR encodings, the Access Flag fault encodings do not follow the Section/Page encoding pattern used for the other TLB-generated faults. However, the Access Flag fault encodings are consistent with the other TLB-generated faults in only using four bits (FSR[3:0]) for their encoding.

Note

All other Fault Status Register encodings are reserved.
The b00011 encoding has been used previously for the Alignment fault. This is very unlikely to cause a problem, because the ARM memory model has changed considerably since that use was deprecated.

If a translation abort occurs during a Data Cache maintenance operation by Virtual Address, then a Data Abort is taken and the DFSR indicates the reason. The FAR indicates the faulting address.

If a translation abort occurs during an Instruction cache maintenance operation by Virtual Address, then a Data Abort is taken, and an Instruction cache maintenance operation fault is indicated in the DFSR. The FAR indicates the faulting address.

Domain and fault address information is only available for data accesses. For instruction aborts R14 must be used to determine the faulting address. You can determine the domain information by performing a TLB lookup for the faulting address and extracting the domain field.

A summary of which abort vector is taken, and which of the Fault Status and Fault Address Registers are updated for each abort type is shown in Table 6.14.

Table 6.14. Summary of aborts

Abort type	Abort taken	Precise?	Register updated?
Abort type	Abort taken	Precise?	IFSR	WFAR	DFSR	FAR
Instruction MMU fault	Prefetch Abort	Yes	Yes	No	No	No
Instruction debug abort	Prefetch Abort	Yes	Yes	No	No	No
Instruction External Abort on translation	Prefetch Abort	Yes	Yes	No	No	No
Instruction External Abort	Prefetch Abort	Yes	Yes	No	No	No
Memory barrier maintenance operation	Data Abort	Yes	Yes	Yes^[a]	Yes	Yes
Data MMU fault	Data Abort	Yes	No	Yes^[a]	Yes	Yes
Data debug abort	Data Abort	No	No	Yes	Yes	Yes^[b]
Data External Abort on translation	Data Abort	Yes	No	Yes^[a]	Yes	Yes
Data External Abort	Data Abort	No^[c]	No	No	Yes	No
Data cache maintenance operation	Data Abort	Yes	No	Yes^[a]	Yes	Yes
^[a]Although the WFAR is updated by the processor the behavior is architecturally Unpredictable. ^[b]The processor updates the FAR with an Unpredictable value. ^[c]Data Aborts can be precise, see External aborts for more details.

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