ARM1136JF-S and ARM1136J-S Technical Reference Manual: 3.3.7. c1, Auxiliary Control Register

3.3.7. c1, Auxiliary Control Register

The purpose of the Auxiliary Control Register is to control:

program flow
cache cleaning
MicroTLB cache strategy
cache size restriction (page coloring).

Note

For more information on how the system control coprocessor operates with caches, see Cache control and configuration.

The Auxiliary Control Register is:

in CP15 c1
a 32-bit read/write register
accessible in privileged mode only.

Figure 3.27 shows the arrangement of bits in the register.

Figure 3.27. Auxiliary Control Register format

Table 3.47 lists the bit functions of the Auxiliary Control Register.

Table 3.47. Auxiliary Control Register field descriptions

Bits	Name	Function
[31:7]	-	Reserved. This field is UNP/RAZ when read. Write as the existing value.
[6]	CZ	Restrict cache size. This bit controls the restriction of cache size to 16KB. Restricting the cache to 16KB allows the processor to run software which does not support ARMv6 page coloring. The value of this bit does not affect the Cache Type Register. For more information see Restrictions on page table mappings (page coloring). 0 = Normal ARMv6 cache behavior. This is the reset value. 1 = Cache size limited to 16KB. The CZ bit is only defined from the rev1 (r1p0) release of the ARM1136JF-S processor. This bit is reserved in earlier releases (UNP/RAZ when read, write as the existing value).
[5]	RV	Disable block transfer cache operations. This bit controls block transfer cache operations: 0 = Block transfer cache operations enabled. This is the reset value. 1 = Block transfer cache operations disabled. If the RV bit is set, attempting a block transfer cache operation will cause an Undefined Instruction exception.
[4]	RA	Disable clean entire data cache. This bit controls the Clean Entire Data Cache and the Clean and Invalidate Entire Data Cache operations: 0 = Clean (and Invalidate) Entire Data Cache operations enabled. This is the reset value. 1 = Clean (and Invalidate) Entire Data Cache operations disabled. If the RA bit is set, attempting a Clean (and Invalidate) Entire Data Cache operation will cause an Undefined Instruction exception.
[3]	TR	MicroTLB random replacement. This bit selects Random replacement for the MicroTLBs if the caches are configured to have Random replacement, using the RR bit in the Control Register, see c1, Control Register. 0 = MicroTLB replacement is Round Robin. This is the reset value. 1 = MicroTLB replacement is Random if cache replacement is also Random.
[2]	SB	Static branch prediction enable. This bit enables the use of static branch prediction if program flow prediction is enabled, using the Z bit of the Control Register, see c1, Control Register. 0 = Static branch prediction is disabled. 1 = Static branch prediction is enabled. This is the reset value.
[1]	DB	Dynamic branch prediction enable. This bit enables the use of dynamic branch prediction if program flow prediction is enabled, using the Z bit of the Control Register, see c1, Control Register. 0 = Dynamic branch prediction is disabled. 1 = Dynamic branch prediction is enabled. This is the reset value.
[0]	RS	Return stack enable. This bit enables the use of the return stack if program flow prediction is enabled, using the Z bit of the Control Register, see c1, Control Register. 0 = Return stack is disabled. 1 = Return stack is enabled. This is the reset value.

Accessing the Auxiliary Control Register

Table 3.48 shows the results of attempted accesses to the Auxiliary Control Register for each mode.

Table 3.48. Results of accesses to the Auxiliary Control Register

Privileged read	Privileged write	User read or write
Data read	Data write	Undefined Instruction exception

Note

You must access this register using a read-modify-write sequence. This enables you to write reserved register bits with their original values.

To access the Auxiliary Control Register you read or write CP15 with:

Opcode_1 set to 0
CRn set to c1
CRm set to c0
Opcode_2 set to 1.

For example:

MRC p15, 0, <Rd>, c1, c0, 1           ; Read Auxiliary Control Register

MCR p15, 0, <Rd>, c1, c0, 1           ; Write Auxiliary Control Register

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