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The tables in this section describe the AHB-Lite interface behavior for instruction side fetches to either Cacheable or Noncacheable regions of memory for the following interface signals:
HBURSTI[2:0]
HTRANSI[1:0]
HADDRI[31:0]
HBSTRBI[7:0]
HUNALIGNI.
See Other AHB-Lite signals for Cacheable and Noncacheable instruction fetches for details of the other AHB-Lite signals.
| Copyright © 2002-2007, 2009 ARM Limited. All rights reserved. | ARM DDI 0211K |
| Non-Confidential | |
| PDF version | |
| Home > Level Two Interface > Instruction Fetch Interface AHB-Lite transfers |