ARM1136JF-S and ARM1136J-S Technical Reference ManualRevision: r1p5
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8.7. DMA Interface AHB-Lite transfers

AHB-Lite reads or writes over the DMA Interface use the standard AHB-Lite signals. The accesses also use the following AHB-Lite signals:

HBURSTD[2:0]

Statically set to Single. Only single transfers are supported.

HTRANSD[1:0]

Normally set to Idle, set to Nonseq to start a transfer.

HRESPD[0]

There is only one response because Retry and Split are not supported.

HUNALIGND

Set if an unaligned transfer is to be carried out.

HBSTRBD[7:0]

One byte lane for each byte in the 64-bit word to be transferred. Each bit is set to indicate that the corresponding byte lane in HRDATAD and HWDATAD is in use.

Note

When the stride is greater than the transaction size and more than one of these transactions falls within a 64-bit transfer, any unaligned access settings of bits [7:0] can be generated within HBSTRBD.

HSIZED[2:0]

Indicates the transfer size, 8, 16, 32, or 64 bits.

HPROTD[4:2]

These bits encode the memory region attributes. Table 8.108 shows the HPROTD[4:2] encodings for the memory region attributes.

Table 8.108. HPROTD[4:2] encoding

HPROTD[4:2]Memory region attribute
b000Strongly Ordered
b001Device
b010Outer Noncacheable
b110Outer Write-Through, No Allocate on Write
b111Outer Write-Back, No Allocate on Write
b011Outer Write-Back, Write Allocate

HPROTD[1]

Indicates whether the transfer type is privileged or User. Usually the transfer type corresponds to the CPSR state of the processor, but a processor in a privileged mode can emulate User mode DMA accesses, see the description of the UM bit in c11, DMA Control Registers. Table 8.109 shows the HPROTD[1] encoding for the transfer.

Table 8.109. HPROTD[1] encoding

HPROTD[1]Transfer type
0User
1Privileged

HPROTD[0]

Indicates that the transfer is an opcode fetch or data access. Table 8.109 shows the HPROTD[0] encoding for the transfer.

Table 8.110. HPROTD[0] encoding

HPROTD[0]Attribute
0 Instruction
1 Data

HSIDEBANDD[3:1]

Encodes the Inner Cacheable TLB attributes. Table 8.111 shows the HSIDEBANDD[3:1] encoding for the Inner Cacheable TLB attributes.

Table 8.111. HSIDEBANDD[3:1] encoding

HSIDEBANDD[3:1]Attribute
b000 Strongly ordered
b001 Device
b010 Inner Noncacheable
b110 Inner Write-Through, No Allocate on Write
b111Inner Write-Back, No Allocate on Write
b011Inner Write-Back, Write Allocate

HSIDEBANDD[0]

Set if the addressed memory region is Shared.

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