| Copyright © 2002-2007, 2009 ARM Limited. All rights reserved. | ARM DDI 0211K |
| Non-Confidential | |
 PDF version | |
| Home > Signal Descriptions > Interrupt signals, including the VIC interface |
| |||
| Home > Signal Descriptions > Interrupt signals, including the VIC interface | |||
Table A.3 lists the interrupt signals, including those used with the VIC interface.
Table A.3. Interrupt signals
| Name | Direction | Description |
|---|---|---|
INTSYNCEN | Input | Indicates that VIC interface is asynchronous. |
IRQACK | Output | Interrupt acknowledge. |
| IRQADDR[31:2] | Input | Address of the IRQ. |
IRQADDRV | Input | Indicates IRQADDR is valid. |
IRQADDRVSYNCEN | Input | Indicates that VIC IRQADDRV requires synchronizer. |
nFIQ | Input | Fast interrupt request.[a] |
nIRQ | Input | Interrupt request.[a] |
nDMAIRQ | Output | Interrupt request by DMA. On reset this pin is set to 1. |
nPMUIRQ | Output | Interrupt request by system performance monitor. On reset this pin is set to 1. |
[a] This signal must be held LOW until an appropriate interrupt response is received from the processor. | ||
| Copyright © 2002-2007, 2009 ARM Limited. All rights reserved. | ARM DDI 0211K |
| Non-Confidential | |
| PDF version | |
| Home > Signal Descriptions > Interrupt signals, including the VIC interface |