ARM1136JF-S and ARM1136J-S Technical Reference Manual: 2.10.3. Load or Store Doubleword

2.10.3. Load or Store Doubleword

The LDREXD and STREXD instructions behave as follows:

The address in memory must be 64-bit aligned, address[2:0] == b000
- An alignment fault is generated if this condition is not met.
  For more information, see Operation of unaligned accesses.
The transaction must be a single access, or an indivisible burst if the bus width is less than 64 bits.

The LDREXD and STREXD instructions share the same data monitors as the LDREX and STREX instructions, a local and a global monitor for each processor, for shared memory support.

`LDREXD`

Figure 2.12 shows the format of the Load Register Doubleword Exclusive, LDREXD, instruction.

Figure 2.12. LDREXD instruction

Syntax

LDREXD{<cond>} <Rd>, [<Rn>]

Operation

if ConditionPassed(cond) then

    processor_id = ExecutingProcessor()

    Rd = Memory[Rn,4]

    R(d+1) = Memory[Rn+4,4]

    physical_address=TLB(Rn)

    if Shared(Rn) ==1 then

        MarkExclusiveGlobal(physical_address,processor_id,8)

    MarkExclusiveLocal(physical_address,processor_id,8)

Notes

For the purpose of endian effects, the transfer is considered as two words, which load from consecutive word-addressed locations in memory.
The result of the LDREXD operation is Unpredictable if:
- you specify register 15 for <Rd+1> or <Rn>
- you specify an odd-numbered register for <Rd>.
If a data abort occurs during an LDREXD operation it is Unpredictable whether the MarkExclusiveGlobal() or the MarkExclusiveLocal() operation is executed. However, Rd and R(d+1) are not updated.
In regions of shared memory which do not support exclusives, the behavior of LDREXD is Unpredictable. This applies to regions of memory which do not have an exclusives monitor implemented.
This command is only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

`STREXD`

Figure 2.13 shows the format of the Store Register Doubleword Exclusive, STREXD, instruction.

Figure 2.13. STREXD instruction

Syntax

STREXD{<cond>} <Rd>, <Rm>, [<Rn>]

Operation

if ConditionPassed(cond) then

    processor_id = ExecutingProcessor()

    physical_address=TLB(Rn)

    if IsExclusiveLocal(physical_address,processor_id,8) then

        if Shared(Rn)==1 then

            if IsExclusiveGlobal(physical_address,processor_id,8) then

                Memory[Rn,4] = Rm

                Memory[Rn+4,4] = R(m+1)

                Rd = 0

                ClearByAddress(physical_address,8)

            else

                Rd =1

        else

            Memory[Rn,4] = Rm

            Memory[Rn+4,4] = R(m+1)

            Rd = 0

    else

        Rd = 1

    ClearExclusiveLocal(processor_id)

Notes

For the purpose of endian effects, the transfer is considered as two words, which store to consecutive word-addressed locations in memory.
There is a register restriction that Rd != Rm, Rd != R(m+1), and Rd != Rn.
The result of the STREXD operation is Unpredictable if you:
- specify register 15 for <Rd>, <Rn> or <Rm+1>
- specify <Rm> as an odd-numbered register.
If a data abort occurs during a STREXD operation:
- Memory is not updated
- <Rd> is not updated
- it is Unpredictable whether the ClearExclusiveLocal() or the ClearByAddress() operation is executed.
In regions of shared memory which do not support exclusives, the behavior of STREXD is Unpredictable. This applies to regions of memory which do not have an exclusives monitor implemented.
This command is only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

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