ARM1136JF-S and ARM1136J-S Technical Reference Manual: 8.5.9. Noncacheable LDM6

8.5.9. Noncacheable `LDM`6

Table 8.56 to Table 8.59 show the values of HTRANSR, HADDRR, HBURSTR, HSIZER, and HBSTRBR for Noncacheable LDM6s from words 0 to 2.

Table 8.60 shows how a Noncacheable LDM6 from words 3 to 7 is split into two operations.

Table 8.56. LDM6 from word 0

HTRANSR	HADDRR	HBURSTR	HSIZER	HBSTRBR
Nseq	`0x00`	Incr	64-bit	b11111111
Seq	`0x08`
Seq	`0x10`

Table 8.57. LDM6 from word 1, Strongly Ordered or Device memory

HTRANSR	HADDRR	HBURSTR	HSIZER	HBSTRBR
Nseq	`0x04`	Incr	32-bit	b11110000
Seq	`0x08`			b00001111
	`0x0C`			b11110000
	`0x10`			b00001111
	`0x14`			b11110000
	`0x18`			b00001111

Table 8.58. LDM6 from word 1, Noncacheable memory or cache disabled

HTRANSR	HADDRR	HBURSTR	HSIZER	HBSTRBR
Nseq	`0x00`	Incr4	64-bit	b11110000^[a]
Seq	`0x08`			b11111111^[a]
	`0x10`			b11111111^[a]
	`0x18`			b00001111^[a]
^[a]Denotes that HUNALIGNR is asserted for that transfer. This is only for ARMv6 unaligned loads and loads to normal memory, where reading more data than is necessary is possible.

Table 8.59. LDM6 from word 2

HTRANSR	HADDRR	HBURSTR	HSIZER	HBSTRBR
Nseq	`0x08`	Incr	64-bit	b11111111
Seq	`0x10`
Seq	`0x18`

Table 8.60. LDM6 from word 3, 4, 5, 6, or 7

Address[4:0]	Operations
`0x0C` (word 3)	`LDM`5 from `0x0C` + `LDR` from `0x00`
`0x10` (word 4)	`LDM`4 from `0x10` + `LDM`2 from `0x00`
`0x14` (word 5)	`LDM`3 from `0x14` + `LDM`3 from `0x00`
`0x18` (word 6)	`LDM`2 from `0x18` + `LDM`4 from `0x00`
`0x1C` (word 7)	`LDR` from `0x1C` + `LDM`5 from `0x00`

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