ARM1136JF-S and ARM1136J-S Technical Reference ManualRevision: r1p5
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ARM1136JF-S™ and ARM1136J-S™ Technical Reference Manual

Revision: r1p5

Copyright © 2002-2007, 2009 ARM Limited. All rights reserved.

Proprietary notices

Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Further reading
Feedback
Feedback on the product
Feedback on this manual
1. Introduction
1.1. About the ARM1136JF-S processor
1.2. Components of the processor
1.2.1. Core
1.2.2. Load Store Unit (LSU)
1.2.3. Prefetch unit
1.2.4. Memory system
1.2.5. Level one memory system
1.2.6. AMBA interface
1.2.7. Coprocessor interface
1.2.8. Debug
1.2.9. Instruction cycle summary and interlocks
1.2.10. Vector Floating-Point (VFP)
1.2.11. System control
1.2.12. Interrupt handling
1.3. Power management
1.4. Configurable options
1.5. Pipeline stages
1.6. Typical pipeline operations
1.6.1. Instruction progression
1.7. ARM1136JF-S architecture with Jazelle technology
1.7.1. Instruction compression
1.7.2. The Thumb instruction set
1.7.3. Java bytecodes
1.8. ARM1136JF-S instruction sets summaries
1.8.1. Extended ARM instruction set summary
1.8.2. Thumb instruction set summary
1.9. Product revisions
2. Programmer’s Model
2.1. About the programmer’s model
2.2. Processor operating states
2.2.1. Switching state
2.2.2. Interworking ARM and Thumb state
2.3. Instruction length
2.4. Data types
2.5. Memory formats
2.5.1. 32-bit word-invariant big-endian format
2.5.2. Little-endian format
2.6. Addresses in an ARM1136JF-S system
2.7. Operating modes
2.8. Registers
2.8.1. The core register set in ARM state
2.8.2. The Thumb state register set
2.8.3. Accessing high registers in Thumb state
2.8.4. ARM state and Thumb state registers relationship
2.9. The program status registers
2.9.1. The condition code flags
2.9.2. The Q flag
2.9.3. The J bit
2.9.4. The GE[3:0] bits
2.9.5. The E bit
2.9.6. The A bit
2.9.7. The control bits
2.9.8. Modification of PSR bits by MSR instructions
2.9.9. Reserved bits
2.10. Additional instructions
2.10.1. Load or Store Byte Exclusive
2.10.2. Load or Store Halfword Exclusive
2.10.3. Load or Store Doubleword
2.10.4. CLREX
2.10.5. NOP - True No Operation
2.11. Exceptions
2.11.1. Changes to existing interrupt vectors
2.11.2. New instructions for exception handling
2.11.3. Exception entry and exit summary
2.11.4. Entering an ARM exception
2.11.5. Leaving an ARM exception
2.11.6. Reset
2.11.7. Fast interrupt request
2.11.8. Interrupt request
2.11.9. Low interrupt latency configuration
2.11.10. Interrupt latency example
2.11.11. Aborts
2.11.12. Imprecise Data Abort mask in the CPSR/SPSR
2.11.13. Software interrupt instruction
2.11.14. Undefined instruction
2.11.15. Breakpoint instruction (BKPT)
2.11.16. Exception vectors
2.11.17. Exception priorities
3. System Control Coprocessor
3.1. About the system control coprocessor
3.1.1. Terms used in this chapter
3.1.2. System control coprocessor functional groups
3.1.3. System control and configuration
3.1.4. MMU control and configuration
3.1.5. Cache control and configuration
3.1.6. TCM control and configuration
3.1.7. Debug access to caches and TLB
3.1.8. DMA control
3.1.9. System performance monitoring
3.1.10. Use of the system control coprocessor
3.2. System control coprocessor registers overview
3.2.1. Register allocation
3.3. System control coprocessor register descriptions
3.3.1. c0, Main ID Register
3.3.2. c0, Cache Type Register
3.3.3. c0, TCM Status Register
3.3.4. c0, TLB Type Register
3.3.5. c0, Core feature ID registers
3.3.6. c1, Control Register
3.3.7. c1, Auxiliary Control Register
3.3.8. c1, Coprocessor Access Control Register
3.3.9. c2, Translation Table Base Register 0, TTBR0
3.3.10. c2, Translation Table Base Register 1, TTBR1
3.3.11. c2, Translation Table Base Control Register, TTBCR
3.3.12. c3, Domain Access Control Register
3.3.13. c5, Data Fault Status Register, DFSR
3.3.14. c5, Instruction Fault Status Register, IFSR
3.3.15. c6, Fault Address Register, FAR
3.3.16. c6, Watchpoint Fault Address Register, WFAR
3.3.17. c7, Cache Operations Register
3.3.18. c8, TLB Operations Register (invalidate TLB operation)
3.3.19. c9, Data and Instruction Cache Lockdown Registers
3.3.20. c9, Data TCM Region Register
3.3.21. c9, Instruction TCM Region Register
3.3.22. c10, TLB Lockdown Register
3.3.23. c10, TEX remap registers
3.3.24. c11, DMA registers overview
3.3.25. c11, DMA Identification and Status Registers
3.3.26. c11, DMA User Accessibility Register
3.3.27. c11, DMA Channel Number Register
3.3.28. c11, DMA Enable Registers
3.3.29. c11, DMA Control Registers
3.3.30. c11, DMA Internal Start Address Registers
3.3.31. c11, DMA External Start Address Registers
3.3.32. c11, DMA Internal End Address Registers
3.3.33. c11, DMA Channel Status Registers
3.3.34. c11, DMA Context ID Registers
3.3.35. c13, FCSE PID Register
3.3.36. c13, Context ID Register
3.3.37. c13, Thread and process ID registers
3.3.38. c15, Memory remap registers
3.3.39. c15, Performance Monitor Control Register (PMNC)
3.3.40. c15, Cycle Counter Register (CCNT)
3.3.41. c15, Count Register 0 (PMN0)
3.3.42. c15, Count Register 1 (PMN1)
3.3.43. c15, Cache debug operations registers
3.3.44. c15, Cache and Main TLB Master Valid Registers
3.3.45. c15, MMU debug operations overview
3.3.46. Registers for MMU debug operations
3.3.47. MMU debugging
4. Unaligned and Mixed-Endian Data Access Support
4.1. About unaligned and mixed-endian support
4.2. Unaligned access support
4.2.1. Word-invariant mode support
4.2.2. ARMv6 extensions
4.2.3. Word-invariant mode and ARMv6 configurations
4.2.4. Word-invariant data access in ARMv6 (U=0)
4.2.5. Support for unaligned data access in ARMv6 (U=1)
4.2.6. ARMv6 unaligned data access restrictions
4.3. Unaligned data access specification
4.3.1. Load unsigned byte, endian independent
4.3.2. Load signed byte, endian independent
4.3.3. Store byte, endian independent
4.3.4. Load unsigned halfword, little-endian
4.3.5. Load unsigned halfword, big-endian
4.3.6. Load signed halfword, little-endian
4.3.7. Load signed halfword, big-endian
4.3.8. Store halfword, little-endian
4.3.9. Store halfword, big-endian
4.3.10. Load word, little-endian
4.3.11. Load word, big-endian
4.3.12. Store word, little-endian
4.3.13. Store word, big-endian
4.3.14. Load double, load multiple, load coprocessor (little-endian, E = 0)
4.3.15. Load double, load multiple, load coprocessor (big-endian, E=1)
4.3.16. Store double, store multiple, store coprocessor (little-endian, E=0)
4.3.17. Store double, store multiple, store coprocessor (big-endian, E=1)
4.4. Operation of unaligned accesses
4.5. Mixed-endian access support
4.5.1. Word-invariant fixed instruction and data endianness
4.5.2. ARMv6 support for mixed-endian data
4.5.3. Reset values of the U, B, and EE bits
4.6. Instructions to reverse bytes in a general-purpose register
4.6.1. All load and store operations
4.7. Instructions to change the CPSR E bit
5. Program Flow Prediction
5.1. About program flow prediction
5.2. Branch prediction
5.2.1. Enabling program flow prediction
5.2.2. Dynamic branch predictor
5.2.3. Static branch predictor
5.2.4. Incorrect predictions and correction
5.3. Return stack
5.4. Instruction Memory Barrier (IMB) instruction
5.4.1. Generic IMB use
5.5. ARM1020T or later IMB implementation
5.5.1. Execution of IMB instructions
6. Memory Management Unit
6.1. About the MMU
6.2. TLB organization
6.2.1. MicroTLB
6.2.2. Main TLB
6.2.3. TLB control operations
6.2.4. Page-based attributes
6.2.5. Supersections
6.3. Memory access sequence
6.3.1. TLB match process
6.3.2. Virtual to physical translation mapping restrictions
6.3.3. Tightly-Coupled Memory
6.4. Enabling and disabling the MMU
6.4.1. Enabling the MMU
6.4.2. Disabling the MMU
6.5. Memory access control
6.5.1. Domains
6.5.2. Access permissions
6.5.3. Execute never bits in the TLB entry
6.6. Memory region attributes
6.6.1. C and B bit, and type extension field encodings
6.6.2. Shared attribute
6.7. Memory attributes and types
6.7.1. Normal memory attribute
6.7.2. Device memory attribute
6.7.3. Shared memory attribute
6.7.4. Strongly Ordered memory attribute
6.7.5. Ordering requirements for memory accesses
6.7.6. Explicit memory barriers
6.7.7. Backwards compatibility
6.8. MMU aborts
6.8.1. External aborts
6.9. MMU fault checking
6.9.1. Fault checking sequence
6.9.2. Alignment fault
6.9.3. Translation fault
6.9.4. Access Flag fault
6.9.5. Domain fault
6.9.6. Permission fault
6.9.7. Debug event
6.10. Fault status and address
6.11. Hardware page table translation
6.11.1. Backwards-compatible page table translation (subpage AP bits enabled)
6.11.2. ARMv6 page table translation (subpage AP bits disabled)
6.11.3. Restrictions on page table mappings (page coloring)
6.12. MMU descriptors
6.12.1. First-level descriptor address
6.12.2. First-level descriptor
6.12.3. Second-level page table walk
6.13. MMU software-accessible registers
6.14. MMU and write buffer
7. Level One Memory System
7.1. About the level one memory system
7.2. Cache organization
7.2.1. Features of the cache system
7.2.2. Cache functional description
7.2.3. Cache control operations
7.2.4. Cache miss handling
7.2.5. Cache disabled behavior
7.2.6. Unexpected hit behavior
7.3. Tightly-coupled memory
7.3.1. SmartCache behavior
7.3.2. Local RAM behavior
7.3.3. Restriction on page table mappings
7.3.4. Restriction on page table attributes
7.4. DMA
7.5. TCM and cache interactions
7.5.1. DMA and core access arbitration
7.5.2. Instruction accesses to TCM
7.5.3. Data and instruction accesses to TCM
7.6. Cache debug
7.7. Write buffer
8. Level Two Interface
8.1. About the level two interface
8.1.1. Level two interface clocking
8.1.2. Level two instruction-side controller
8.1.3. Level two data-side controller
8.1.4. DMA
8.2. Synchronization primitives
8.2.1. Load exclusive instruction
8.2.2. Store exclusive instruction
8.2.3. Example of LDREX and STREX usage
8.3. AHB-Lite control signals in the ARM1136JF-S processor
8.3.1. Signal name suffixes
8.3.2. HTRANS[1:0]
8.3.3. HSIZE[2:0]
8.3.4. HBURST[2:0]
8.3.5. HPROT[4:0]
8.3.6. HPROT[5] and HRESP[2]
8.3.7. HBSTRB[7:0] and HUNALIGN
8.3.8. Exclusive access timing
8.4. Instruction Fetch Interface AHB-Lite transfers
8.4.1. Cacheable fetches
8.4.2. Noncacheable fetches
8.4.3. Other AHB-Lite signals for Cacheable and Noncacheable instruction fetches
8.5. Data Read Interface AHB-Lite transfers
8.5.1. Linefills
8.5.2. Noncacheable LDRB
8.5.3. Noncacheable LDRH
8.5.4. Noncacheable LDR or LDM1
8.5.5. Noncacheable LDRD or LDM2
8.5.6. Noncacheable LDM3
8.5.7. Noncacheable LDM4
8.5.8. Noncacheable LDM5
8.5.9. Noncacheable LDM6
8.5.10. Noncacheable LDM7
8.5.11. Noncacheable LDM8
8.5.12. Noncacheable LDM9
8.5.13. Noncacheable LDM10
8.5.14. Noncacheable LDM11
8.5.15. Noncacheable LDM12
8.5.16. Noncacheable LDM13
8.5.17. Noncacheable LDM14
8.5.18. Noncacheable LDM15
8.5.19. Noncacheable LDM16
8.5.20. SWP instructions
8.5.21. Page table walks
8.5.22. Other AHB-Lite signals for Data Read ports
8.6. Data Write Interface AHB-Lite transfers
8.6.1. Stores on the AHB-Lite interface
8.6.2. Half-line write-back
8.6.3. Full-line write-back
8.6.4. Store-exclusive
8.6.5. Other AHB-Lite signals for Data Write port
8.7. DMA Interface AHB-Lite transfers
8.8. Peripheral Interface AHB-Lite transfers
8.8.1. Reads and writes
8.8.2. Other AHB-Lite signals for Peripheral Interface reads and writes
8.9. AHB-Lite
8.9.1. Specification
8.9.2. Compatibility
8.9.3. AHB-Lite master interface
8.9.4. AHB-Lite advantages
8.9.5. AHB-Lite conversion to full AHB
8.9.6. AHB-Lite slaves
8.9.7. Block diagram
9. Clocking and Resets
9.1. Clocking
9.1.1. Synchronous clocking
9.1.2. Asynchronous clocking
9.1.3. Synchronization
9.1.4. Read latency penalty for synchronous operation
9.2. Reset
9.3. Reset modes
9.3.1. Power-on reset
9.3.2. CP14 debug logic
9.3.3. Processor reset, nRESETIN
9.3.4. HRESETPDn reset
9.3.5. HRESETIRWn reset
9.3.6. DBGTAP reset
9.3.7. Normal operation
10. Power Control
10.1. About power control
10.2. Power management
10.2.1. Run mode
10.2.2. Standby mode
10.2.3. Shutdown mode
10.2.4. Dormant mode
10.2.5. Communication to the Power Management Controller
11. Coprocessor Interface
11.1. About the coprocessor interface
11.2. Coprocessor pipeline
11.2.1. Coprocessor instructions
11.2.2. Coprocessor control
11.2.3. Pipeline synchronization
11.2.4. Pipeline control
11.2.5. Instruction tagging
11.2.6. Flush broadcast
11.3. Token queue management
11.3.1. Queue implementation
11.3.2. Queue modification
11.3.3. Queue flushing
11.4. Token queues
11.4.1. Instruction queue
11.4.2. Length queue
11.4.3. Accept queue
11.4.4. Cancel queue
11.4.5. Finish queue
11.5. Data transfer
11.5.1. Loads
11.5.2. Stores
11.6. Operations
11.6.1. Normal operation
11.6.2. Cancel operations
11.6.3. Bounce operations
11.6.4. Flush operations
11.6.5. Retirement operations
11.7. Multiple coprocessors
11.7.1. Interconnect considerations
11.7.2. Coprocessor selection
11.7.3. Coprocessor switching
12. Vectored Interrupt Controller Port
12.1. About the PL192 Vectored Interrupt Controller
12.2. About the ARM1136JF-S VIC port
12.2.1. Synchronization of the VIC port signals
12.2.2. Interrupt handler exit
12.3. Timing of the VIC port
12.3.1. PL192 VIC timing
12.3.2. Core timing
12.4. Interrupt entry flowchart
13. Debug
13.1. Debug systems
13.1.1. The debug host
13.1.2. The protocol converter
13.1.3. The ARM1136JF-S processor
13.2. About the debug unit
13.2.1. Halting debug-mode debugging
13.2.2. Monitor debug-mode debugging
13.2.3. Virtual Addresses and debug
13.2.4. Programming the debug unit
13.3. Debug registers
13.3.1. Accessing debug registers
13.3.2. Debug register descriptions
13.3.3. CP14 c0, Debug ID Register (DIDR)
13.3.4. CP14 c1, Debug Status and Control Register (DSCR)
13.3.5. CP14 c5, Data Transfer Registers (DTR)
13.3.6. CP14 c7, Vector Catch Register (VCR)
13.3.7. Overview of breakpoint and watchpoint registers on the ARM1136JF-S processor
13.3.8. CP14 c64-c69, Breakpoint Value Registers (BVR)
13.3.9. CP14 c80-c85, Breakpoint Control Registers (BCR)
13.3.10. CP14 c96-c97, Watchpoint Value Registers (WVR)
13.3.11. CP14 c112-c113, Watchpoint Control Registers (WCR)
13.4. CP14 registers reset
13.5. CP14 debug instructions
13.5.1. Executing CP14 debug instructions
13.6. Debug events
13.6.1. Software debug event
13.6.2. External debug request signal
13.6.3. Halt DBGTAP instruction
13.6.4. Behavior of the processor on debug events
13.6.5. Effect of a debug event on CP15 registers
13.7. Debug exception
13.8. Debug state
13.8.1. Behavior of the PC in Debug state
13.8.2. Interrupts
13.8.3. Exceptions
13.9. Debug communications channel
13.10. Debugging in a cached system
13.10.1. Data Cache writes
13.11. Debugging in a system with TLBs
13.12. Monitor debug-mode debugging
13.12.1. Entering the monitor target
13.12.2. Setting breakpoints, watchpoints, and vector catch debug events
13.12.3. Setting software breakpoint debug events (BKPT instructions)
13.12.4. Using the debug communications channel
13.13. Halting debug-mode debugging
13.13.1. Entering Debug state
13.13.2. Exiting Debug state
13.13.3. Programming debug events
13.14. External signals
14. Debug Test Access Port
14.1. Debug Test Access Port and Halting debug-mode
14.2. Synchronizing RealView ICE
14.3. Entering Debug state
14.4. Exiting Debug state
14.5. The DBGTAP port and debug registers
14.6. Debug registers
14.6.1. Bypass register
14.6.2. Device ID code register
14.6.3. Instruction Register
14.6.4. Scan chain select register (SCREG)
14.6.5. Scan chains
14.6.6. Reset
14.7. Using the Debug Test Access Port
14.7.1. Entering and leaving Debug state
14.7.2. Executing instructions in Debug state
14.7.3. Using the ITRsel IR instruction
14.7.4. Transferring data between the host and the core
14.7.5. Using the debug communications channel
14.7.6. Target to host debug communications channel sequence
14.7.7. Host to target debug communications channel
14.7.8. Transferring data in Debug state
14.7.9. Example sequences
14.8. Debug sequences
14.8.1. Debug macros
14.8.2. General setup
14.8.3. Forcing the processor to halt
14.8.4. Entering Debug state
14.8.5. Leaving Debug state
14.8.6. Reading a current mode ARM register in the range R0-R14
14.8.7. Writing a current mode ARM register in the range R0-R14
14.8.8. Reading the CPSR/SPSR
14.8.9. Writing the CPSR/SPSR
14.8.10. Reading the PC
14.8.11. Writing the PC
14.8.12. General notes about reading and writing memory
14.8.13. Reading memory as words
14.8.14. Writing memory as words
14.8.15. Reading memory as halfwords or bytes
14.8.16. Writing memory as halfwords/bytes
14.8.17. Coprocessor register reads and writes
14.8.18. Reading coprocessor registers
14.8.19. Writing coprocessor registers
14.9. Programming debug events
14.9.1. Reading registers using scan chain 7
14.9.2. Writing registers using scan chain 7
14.9.3. Setting breakpoints, watchpoints and vector catches
14.9.4. Setting software breakpoints
14.10. Monitor debug-mode debugging
14.10.1. Receiving data from the core
14.10.2. Sending data to the core
15. Trace Interface Port
15.1. About the ETM interface
15.1.1. Instruction interface
15.1.2. Data address interface
15.1.3. Data value interface
15.1.4. Pipeline advance interface
15.1.5. Coprocessor interface
15.1.6. Other connections to the core
16. Cycle Timings and Interlock Behavior
16.1. About cycle timings and interlock behavior
16.1.1. Changes in instruction flow overview
16.1.2. Definition of terms
16.1.3. Instruction execution overview
16.1.4. Conditional instructions
16.1.5. Opposite condition code checks
16.2. Register interlock examples
16.3. Data processing instructions
16.3.1. Cycle counts if destination is not the PC
16.3.2. Cycle counts if destination is the PC
16.3.3. Example interlocks
16.4. QADD, QDADD, QSUB, and QDSUB instructions
16.5. ARMv6 media data processing
16.6. ARMv6 Sum of Absolute Differences (SAD)
16.6.1. Example interlocks
16.7. Multiplies
16.8. Branches
16.9. Processor state updating instructions
16.10. Single load and store instructions
16.10.1. Base register update
16.11. Load and store double instructions
16.12. Load and store multiple instructions
16.12.1. Load and store multiples, other than load multiples including the PC
16.12.2. Load multiples, where the PC is in the register list
16.12.3. Example interlocks
16.13. RFE and SRS instructions
16.14. Synchronization instructions
16.15. Coprocessor instructions
16.16. No operation instruction
16.17. SWI, BKPT, Undefined, and Prefetch Aborted instructions
16.18. Thumb instructions
17. AC Characteristics
17.1. ARM1136JF-S timing diagrams
17.2. ARM1136JF-S timing parameters
A. Signal Descriptions
A.1. Global signals
A.2. Static configuration signals
A.3. Interrupt signals, including the VIC interface
A.4. AHB interface signals
A.4.1. Instruction fetch port signals
A.4.2. Data read port signals
A.4.3. Data write port
A.4.4. Peripheral port signals
A.4.5. DMA port signals
A.5. Coprocessor interface signals
A.6. Debug interface signals, including JTAG
A.7. ETM interface signals
A.8. Test signals
B. Functional changes in the rev1 (r1pn) releases
B.1. New instructions
B.1.1. Synchronization instructions
B.1.2. Other instructions
B.2. Changes to unaligned access support
B.3. Memory system architecture changes
B.3.1. Removal of page coloring restrictions
B.3.2. Changes to access permissions
B.3.3. Implementation of an Access Flag and Access Flag fault detection
B.3.4. TEX remap
B.4. Debug changes
B.5. VFP changes, ARM1136JF-S only
B.6. Effects on coprocessor CP15
B.6.1. Register 0: CPU ID registers
B.6.2. Register 1, System control registers
B.6.3. Register 5, Fault status registers
B.6.4. Register 10, TLB lockdown and remapping registers
B.6.5. Register 13, Process, Thread ID and Processor ID registers
C. Revisions
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. ARM1136JF-S processor block diagram
1.2. ARM1136 pipeline stages
1.3. Typical operations in pipeline stages
1.4. Pipeline for a typical ALU operation
1.5. Pipeline for a typical multiply operation
1.6. Pipeline progression of an LDR or STR operation
1.7. Pipeline progression of an LDM or STM operation
1.8. Pipeline progression of an LDR that misses
2.1. Big-endian addresses of the bytes in words
2.2. Little-endian addresses of the bytes in words
2.3. Register organization in ARM state
2.4. ARM core register set showing register banking
2.5. Register organization in Thumb state
2.6. ARM state and Thumb state registers relationship
2.7. Program Status Register format
2.8. LDREXB instruction
2.9. STREXB instructions
2.10. LDREXH instruction
2.11. STREXH instruction
2.12. LDREXD instruction
2.13. STREXD instruction
2.14. CLREX instruction
2.15. NOP instruction
3.1. System control and configuration registers
3.2. MMU control and configuration registers
3.3. Cache control and configuration registers
3.4. TCM control and configuration registers
3.5. Debug access to caches and TLB registers
3.6. DMA control and configuration registers
3.7. System performance monitor registers
3.8. CP15 MRC and MCR bit pattern
3.9. Main ID Register format
3.10. Cache Type Register format
3.11. Dsize and Isize field format
3.12. TCM Status Register format
3.13. TLB Type Register format
3.14. Processor Feature Register 0 format
3.15. Processor Feature Register 1 format
3.16. Debug Feature Register 0 format
3.17. Memory Model Feature Register 0 format
3.18. Memory Model Feature Register 1 format
3.19. Memory Model Feature Register 2 format
3.20. Memory Model Feature Register 3 format
3.21. Instruction Set Attributes Register 0 format
3.22. Instruction Set Attributes Register 1 format
3.23. Instruction Set Attributes Register 2 format
3.24. Instruction Set Attributes Register 3 format
3.25. Instruction Set Attributes Register 4 format
3.26. Control Register format
3.27. Auxiliary Control Register format
3.28. Coprocessor Access Control Register format
3.29. Translation Table Base Register 0 format
3.30. Translation Table Base Register 1 format
3.31. Translation Table Base Control Register format
3.32. Domain Access Control Register format
3.33. Data Fault Status Register format
3.34. Instruction Fault Status Register format
3.35. Cache Operations Register operations using MCR or MRC instructions
3.36. Cache Operations Register operations using MCRR instructions
3.37. CP15 c7 Register format for Set/Way operations
3.38. Usual CP15 c7 Register format for MVA operations
3.39. CP15 c7 register MVA format for Flush Branch Target Cache Entry operation
3.40. Block address format
3.41. Cache Dirty Status Register format
3.42. Block Transfer Status Register format
3.43. TLB Operations Register format for Invalidate Entry by MVA
3.44. TLB Operations Register format for Invalidate Entry on ASID Match
3.45. Instruction and Data Cache Lockdown Registers format
3.46. Data TCM Region Register format
3.47. Instruction TCM Region Register format
3.48. TLB Lockdown Register format
3.49. Primary Region Remap Register format
3.50. Normal Memory Remap Register format
3.51. DMA Identification and Status Registers format
3.52. DMA User Accessibility Register format
3.53. DMA Channel Number Register format
3.54. DMA Control Register format
3.55. DMA Channel Status Register format
3.56. DMA Context ID Register format
3.57. FCSE PID Register format
3.58. Address mapping using CP15 c13
3.59. Context ID Register format
3.60. Instruction, Data, and DMA Memory Remap Registers format
3.61. Peripheral Port Memory Remap Register format
3.62. Performance Monitor Control Register format
3.63. Cache debug operations registers
3.64. Cache Debug Control Register format
3.65. Instruction and Data Debug Cache Register format
3.66. Instruction Cache Data RAM Read Operation Register format
3.67. Tag RAM Read Operation Register format
3.68. Cache and Main TLB Master Valid Registers
3.69. Registers for MMU debug operations
3.70. MicroTLB Index Register format
3.71. Main TLB Index Register format
3.72. TLB VA Registers format
3.73. TLB VA Registers memory space identifier format
3.74. TLB PA Registers format
3.75. Main TLB Attribute Register format
3.76. MicroTLB Attribute Registers format
3.77. TLB Debug Control Register format
4.1. Load unsigned byte
4.2. Load signed byte
4.3. Store byte
4.4. Load unsigned halfword, little-endian
4.5. Load unsigned halfword, big-endian
4.6. Load signed halfword, little-endian
4.7. Load signed halfword, big-endian
4.8. Store halfword, little-endian
4.9. Store halfword, big-endian
4.10. Load word, little-endian
4.11. Load word, big-endian
4.12. Store word, little-endian
4.13. Store word, big-endian
6.1. Translation table managed TLB fault checking sequence, part 1
6.2. Descriptor checking for Translation table managed TLB fault checking, level 1 and level 2
6.3. Translation table managed TLB fault checking sequence, part 2
6.4. Backwards-compatible first-level descriptor format
6.5. Backwards-compatible second-level descriptor format
6.6. Backwards-compatible section, supersection, and page translation
6.7. ARMv6 first-level descriptor formats with subpages enabled
6.8. ARMv6 first-level descriptor formats with subpages disabled
6.9. ARMv6 second-level descriptor format
6.10. ARMv6 section, supersection, and page translation
6.11. Generating a first-level descriptor address
6.12. Translation for a 1MB section, ARMv6 format
6.13. Translation for a 1MB section, backwards-compatible format
6.14. Generating a second-level page table address
6.15. Large page table walk, ARMv6 format
6.16. Large page table walk, backwards-compatible format
6.17. 4KB small page or 1KB small subpage translations, backwards-compatible
6.18. 4KB extended small page translations, ARMv6 format
6.19. 4KB extended small page or 1KB extended small subpage translations, backwards-compatible
7.1. Level one cache block diagram
8.1. Level two interconnect interfaces
8.2. Synchronization penalty
8.3. Exclusive access read and write with Okay response
8.4. Exclusive access read and write with Xfail response
8.5. Exclusive access read and write with Xfail response and following transfer
8.6. AHB-Lite single-master system
8.7. AHB-Lite block diagram
9.1. Synchronization between AHB and core clock domains
9.2. Synchronization between core and AHB clock domains
9.3. Read latency for synchronous 1:1 clocking
9.4. Power-on reset
11.1. Core and coprocessor pipelines
11.2. Coprocessor pipeline and queues
11.3. Coprocessor pipeline
11.4. Token queue buffers
11.5. Queue reading and writing
11.6. Queue flushing
11.7. Instruction queue
11.8. Coprocessor data transfer
11.9. Instruction iteration for loads
11.10. Load data buffering
12.1. Connection of a PL192 VIC to an ARM1136 processor
12.2. VIC port timing example
12.3. Interrupt entry sequence
13.1. Typical debug system
13.2. Debug registers
13.3. Debug ID Register format
13.4. Debug Status and Control Register format
13.5. Core restarted and Core halted bits
13.6. Data Transfer Registers format
13.7. Vector Catch Register format
13.8. Breakpoint Value Registers BVR0 to BVR3 format
13.9. Breakpoint Value Registers BVR4 and BVR5 format
13.10. Breakpoint Control Registers format
13.11. Watchpoint Value Registers format
13.12. Watchpoint Control Registers format
14.1. JTAG DBGTAP state machine diagram
14.2. RealView ICE clock synchronization
14.3. Bypass register operation
14.4. Device ID code register operation
14.5. Instruction Register operation
14.6. Scan Chain Select Register operation
14.7. Scan chain 0 operation
14.8. Scan chain 1 operation
14.9. Scan chain 4 operation
14.10. Scan chain 5 operation, EXTEST selected
14.11. Scan chain 5 operation, INTEST selected
14.12. Scan chain 6 operation
14.13. Scan chain 7 operation
14.14. Behavior of the ITRsel IR instruction
15.1. ETMCPADDRESS encoding

List of Tables

1.1. Double-precision VFP operations
1.2. Flush-to-zero mode
1.3. Configurable options
1.4. ARM1136JF-S processor default configurations
1.5. Key to instruction set tables
1.6. ARM instruction set summary
1.7. Addressing mode 2
1.8. Addressing mode 2P, post-indexed only
1.9. Addressing mode 3
1.10. Addressing mode 4L, for load operations
1.11. Addressing mode 4S, for store operations
1.12. Addressing mode 5
1.13. Operand2
1.14. Fields
1.15. Condition codes
1.16. Thumb instruction set summary
2.1. Address types in an ARM1136JF-S system
2.2. Register mode identifiers
2.3. GE[3:0] settings
2.4. PSR mode bit values
2.5. Exception entry and return
2.6. Configuration of exception vector address locations
2.7. Exception vectors
3.1. System control coprocessor register functions
3.2. Summary of CP15 registers and operations
3.3. Summary of CP15 MCRR operations
3.4. Main ID Register field descriptions
3.5. Results of accesses to the Main ID Register
3.6. Cache Type Register field descriptions
3.7. Ctype field encoding
3.8. Dsize and Isize field summary
3.9. Cache size encoding (M=0)
3.10. Cache associativity encoding (M=0)
3.11. Line length encoding
3.12. Results of accesses to the Cache Type Register 0
3.13. Example Cache Type Register format
3.14. TCM Status Register field descriptions
3.15. Results of accesses to the TCM Status Register
3.16. TLB Type Register field descriptions
3.17. Results of accesses to the TCM Status Register
3.18. Processor Feature Register 0 bit functions
3.19. Results of accesses to the Processor Feature Register 0
3.20. Processor Feature Register 1 bit functions
3.21. Results of accesses to the Processor Feature Register 1
3.22. Debug Feature Register 0 bit functions
3.23. Results of accesses to the Debug Feature Register 0
3.24. Results of accesses to the Auxiliary Feature Register 0
3.25. Memory Model Feature Register 0 bit functions
3.26. Results of accesses to the Memory Model Feature Register 0
3.27. Memory Model Feature Register 1 bit functions
3.28. Results of accesses to the Memory Model Feature Register 1
3.29. Memory Model Feature Register 2 bit functions
3.30. Results of accesses to the Memory Model Feature Register 2
3.31. Memory Model Feature Register 3 bit functions
3.32. Results of accesses to the Memory Model Feature Register 3
3.33. Instruction Set Attributes Register 0 bit functions
3.34. Results of accesses to the Instruction Set Attributes Register 0
3.35. Instruction Set Attributes Register 1 bit functions
3.36. Results of accesses to the Instruction Set Attributes Register 1
3.37. Instruction Set Attributes Register 2 bit functions
3.38. Results of accesses to the Instruction Set Attributes Register 2
3.39. Instruction Set Attributes Register 3 bit functions
3.40. Results of accesses to the Instruction Set Attributes Register 3
3.41. Instruction Set Attributes Register 4 bit functions
3.42. Results of accesses to the Instruction Set Attributes Register 4
3.43. Results of accesses to the Instruction Set Attributes Register 5
3.44. Control Register bit functions
3.45. B bit, U bit, and EE bit settings, and Control Register reset value
3.46. Results of accesses to the Control Register
3.47. Auxiliary Control Register field descriptions
3.48. Results of accesses to the Auxiliary Control Register
3.49. Coprocessor Access Control Register field descriptions
3.50. Coprocessor access rights encodings
3.51. Results of accesses to the Coprocessor Access Control Register
3.52. Translation Table Base Register 0 field descriptions
3.53. Results of accesses to the Translation Table Base Register 0
3.54. Translation Table Base Register 1 field descriptions
3.55. Results of accesses to the Translation Table Base Register 1
3.56. Values of N for Translation Table Base Register 0
3.57. Results of accesses to the Translation Table Base Control Register
3.58. Domain Access Control Register field descriptions
3.59. Encoding of domain access control fields in the Domain Access Control Register
3.60. Results of accesses to the Domain Access Control Register
3.61. Data Fault Status Register bits
3.62. DFSR fault status encoding
3.63. Results of accesses to the Data Fault Status Register
3.64. Instruction Fault Status Register bits
3.65. IFSR fault status encoding
3.66. Results of accesses to the Instruction Fault Status Register
3.67. Results of accesses to the Fault Address Register
3.68. Results of accesses to the Watchpoint Fault Address Register
3.69. Results of attempting privileged mode, write-only CP15 c7 instructions
3.70. Results of attempting privileged mode, read-only CP15 c7 instruction
3.71. Results of attempting user mode, write-only CP15 c7 instructions
3.72. Results of attempting user mode, read-only CP15 c7 instruction
3.73. Bit fields for Set/Way operations using CP15 c7
3.74. Cache size and S value dependency
3.75. Bit fields for MVA operations using CP15 c7
3.76. Cache operations for entire cache
3.77. Cache operations for single lines
3.78. Cache operations for address ranges
3.79. CP15 c7 block transfer operations
3.80. Cache Dirty Status Register bit functions
3.81. Results of accesses to the Cache Dirty Status Register
3.82. Cache operations flush functions
3.83. Results of accesses to the Data Synchronization Barrier operation
3.84. Results of accesses to the Data Memory Barrier operation
3.85. Results of accesses to the Wait For Interrupt operation
3.86. CP15 Register c7 block transfer control MCR/MRC operations
3.87. Block Transfer Status Register bit functions
3.88. Results of accesses to the Block Transfer Status Register
3.89. Results of accesses to the Stop Prefetch Range operation
3.90. Results of accesses to the TLB Operations Register
3.91. Instruction and data cache lockdown register bit functions
3.92. Results of accesses to the Cache Lockdown Registers
3.93. Data TCM Region Register bit functions
3.94. Size field encoding for Data TCM Region Register
3.95. Results of accesses to the Data TCM Region Register
3.96. Instruction TCM Region Register bit functions
3.97. Size field encoding for Instruction TCM Region Register
3.98. Results of accesses to the Instruction TCM Region Register
3.99. TLB Lockdown Register bit functions
3.100. Results of accesses to the Data TLB Lockdown Register
3.101. Primary Region Remap Register bit functions
3.102. Encoding for the remapping of the primary memory type
3.103. Normal Memory Remap Register bit functions
3.104. Remap encoding for Inner or Outer cacheable attributes
3.105. Results of access to the memory region remap registers
3.106. Page table format TEX[0], C and B bit encodings when TRE=1
3.107. DMA registers
3.108. DMA identification and status register bit functions
3.109. DMA Identification and Status Register functions
3.110. Results of accesses to the DMA Identification and Status Registers
3.111. DMA User Accessibility Register bit functions
3.112. Results of accesses to the DMA User Accessibility Register
3.113. DMA Channel Number Register bit functions
3.114. Results of accesses to the DMA Channel Number Register
3.115. Results of accesses to the DMA Enable Registers
3.116. DMA Enable Register selection
3.117. DMA Control Register bit functions
3.118. Results of accesses to the DMA Control Registers
3.119. Results of accesses to a DMA Internal Start Address Register
3.120. Results of accesses to a DMA External Start Address Register
3.121. Results of accesses to a DMA Internal End Address Register
3.122. DMA Channel Status Register bit functions
3.123. Results of accesses to a DMA Channel Status Register
3.124. DMA Context ID Register bit functions
3.125. Results of accesses to the DMA Context ID Register
3.126. FCSE PID Register bit functions
3.127. Results of accesses to the FCSE PID Register
3.128. Context ID Register bit functions
3.129. Results of accesses to the Context ID Register
3.130. Results of access to the thread and process ID registers
3.131. Instruction, Data and DMA Memory Remap Register bit functions
3.132. Memory remap registers - outer region remap encoding
3.133. Memory remap registers - inner region remap encoding
3.134. Peripheral Port Memory Remap Register bit functions
3.135. Peripheral Port Memory Remap Register Size field encoding
3.136. Results of accesses to the Memory Remap Registers
3.137. Default memory regions when MMU is disabled
3.138. Performance Monitor Control Register bit functions
3.139. PMNC flag values
3.140. Results of accesses to the Performance Monitor Control Register
3.141. Performance monitoring events
3.142. Results of accesses to the Cycle Count Register
3.143. Results of accesses to the Count Register 0
3.144. Results of accesses to the Count Register 1
3.145. Cache debug CP15 operations
3.146. Cache Debug Control Register bit functions
3.147. Results of accesses to the Cache Debug Control Register
3.148. Construction of the Tag address
3.149. Results of accesses to the Instruction and Data Debug Cache Registers
3.150. Results of accesses to the Instruction and Data Debug Cache Registers
3.151. Cache debug CP15 operations
3.152. Cache and Main TLB Master Valid Registers summary
3.153. Results of accesses to the Instruction Cache and Instruction SmartCache Master Valid Registers
3.154. Results of accesses to the Data Cache and Data SmartCache Master Valid Registers
3.155. Results of accesses to the Main TLB Master Valid Registers
3.156. MicroTLB Index Registers bit functions
3.157. Results of accesses to the Instruction MicroTLB and Data MicroTLB Index Registers
3.158. Main TLB Entry Registers bit functions
3.159. Results of accesses to the Main TLB Entry Registers
3.160. TLB VA Registers bit functions
3.161. TLB VA Register Index bits
3.162. Results of accesses to the Data MicroTLB VA and Instruction MicroTLB VA Registers
3.163. Results of accesses to the Main TLB VA Register
3.164. TLB PA Registers bit functions
3.165. TLB PA Registers SZ field encoding
3.166. TLB PA Registers XRGN field encoding
3.167. TLB PA Registers AP field encoding
3.168. Results of accesses to the Data MicroTLB PA and Instruction MicroTLB PA Registers
3.169. Results of accesses to the Main TLB PA Register
3.170. TLB Attribute Registers bit functions
3.171. Upper subpage access permission field encoding
3.172. RGN field encoding
3.173. Results of accesses to the Data MicroTLB Attribute and Instruction MicroTLB Attribute Registers
3.174. Results of accesses to the Main TLB Attribute Register
3.175. TLB Debug Control Register bit functions
3.176. Results of accesses to the TLB Debug Control Register
3.177. MicroTLB and main TLB debug operations
4.1. Unaligned access handling
4.2. Access type descriptions
4.3. Alignment fault occurrence when access behavior is architecturally unpredictable
4.4. Word-invariant endianness using CP15 c1
4.5. Mixed-endian configuration
4.6. B bit, U bit, and EE bit settings
6.1. Access permission bit encoding
6.2. Access permission encodings when S and R bits are used
6.3. Page table format TEX[2:0], C and B bit encodings when TRE=0
6.4. Cache policy bits
6.5. Inner and Outer cache policy implementation options
6.6. Page table format TEX[0], C and B bit encodings when TRE=1
6.7. Primary region memory type encodings
6.8. Cache attribute encodings for remapped regions
6.9. Remapping of the shareable attribute
6.10. Memory attributes
6.11. Memory ordering restrictions
6.12. Memory region backwards compatibility
6.13. Fault Status Register encoding
6.14. Summary of aborts
6.15. Translation table size
6.16. Access types from first-level descriptor bit values
6.17. Access types from second-level descriptor bit values
6.18. CP15 register functions
7.1. Summary of data accesses to TCM and caches
7.2. Summary of instruction accesses to TCM and caches
8.1. HTRANS[1:0] settings
8.2. HSIZE[2:0] encoding
8.3. HBURST[2:0] settings
8.4. HPROT[1:0] encoding
8.5. HPROT[4:2] encoding
8.6. HRESP[2:0] mnemonics
8.7. Mapping of HBSTRB to HWDATA bits for a 64-bit interface
8.8. Byte lane strobes for example ARMv6 transfers
8.9. AHB-Lite signals for Cacheable fetches
8.10. AHB-Lite signals for Noncacheable fetches
8.11. HPROTI[4:2] encoding
8.12. HPROTI[1] encoding
8.13. HSIDEBANDI[3:1] encoding
8.14. Linefills
8.15. LDRB
8.16. LDRH
8.17. LDR or LDM1
8.18. LDRD or LDM2 from word 0
8.19. LDRD or LDM2 from word 1
8.20. LDRD or LDM2 from word 2
8.21. LDRD or LDM2 from word 3
8.22. LDRD or LDM2 from word 4
8.23. LDRD or LDM2 from word 5
8.24. LDRD or LDM2 from word 6
8.25. LDRD or LDM2 from word 7
8.26. LDM3 from word 0, Strongly Ordered or Device memory
8.27. LDM3 from word 0, Noncacheable memory or cache disabled
8.28. LDM3 from word 1, Strongly Ordered or Device memory
8.29. LDM3 from word 1,Noncacheable memory or cache disabled
8.30. LDM3 from word 2,Strongly Ordered or Device memory
8.31. LDM3 from word 2, Noncacheable memory or cache disabled
8.32. LDM3 from word 3, Strongly Ordered or Device memory
8.33. LDM3 from word 3, Noncacheable memory or cache disabled
8.34. LDM3 from word 4, Strongly Ordered or Device memory
8.35. LDM3 from word 4, Noncacheable memory or cache disabled
8.36. LDM3 from word 5, Strongly Ordered or Device memory
8.37. LDM3 from word 5, Noncacheable memory or cache disabled
8.38. LDM3 from word 6 or 7, Noncacheable memory or cache disabled
8.39. LDM4 from word 0
8.40. LDM4 from word 1, Strongly Ordered or Device memory
8.41. LDM4 from word 1, Noncacheable memory or cache disabled
8.42. LDM4 from word 2
8.43. LDM4 from word 3, Strongly Ordered or Device memory
8.44. LDM4 from word 3, Noncacheable memory or cache disabled
8.45. LDM4 from word 4
8.46. LDM4 from word 5, 6, or 7
8.47. LDM5 from word 0, Strongly Ordered or Device memory
8.48. LDM5 from word 0, Noncacheable memory or cache disabled
8.49. LDM5 from word 1, Strongly Ordered or Device memory
8.50. LDM5 from word 1, Noncacheable memory or cache disabled
8.51. LDM5 from word 2, Strongly Ordered or Device memory
8.52. LDM5 from word 2, Noncacheable memory or cache disabled
8.53. LDM5 from word 3, Strongly Ordered or Device memory
8.54. LDM5 from word 3, Noncacheable memory or cache disabled
8.55. LDM5 from word 4, 5, 6, or 7
8.56. LDM6 from word 0
8.57. LDM6 from word 1, Strongly Ordered or Device memory
8.58. LDM6 from word 1, Noncacheable memory or cache disabled
8.59. LDM6 from word 2
8.60. LDM6 from word 3, 4, 5, 6, or 7
8.61. LDM7 from word 0, Strongly Ordered or Device memory
8.62. LDM7 from word 0, Noncacheable memory or cache disabled
8.63. LDM7 from word 1, Strongly Ordered or Device memory
8.64. LDM7 from word 1, Noncacheable memory or cache disabled
8.65. LDM7 from word 2, 3, 4, 5, 6, or 7
8.66. LDM8 from word 0
8.67. LDM8 from word 1, 2, 3, 4, 5, 6, or 7
8.68. LDM9
8.69. LDM10
8.70. LDM11
8.71. LDM12
8.72. LDM13
8.73. LDM14
8.74. LDM15
8.75. LDM16
8.76. Cacheable swap
8.77. Noncacheable swap
8.78. Page table walks
8.79. HSIDEBAND[3:1] encoding
8.80. STRB
8.81. STRH
8.82. STR or STM1
8.83. STRD or STM2 to words 0, 1, 2, 3, 4, 5, or 6
8.84. STRD or STM2 to word 7
8.85. STM3 to words 0, 1, 2, 3, 4, or 5
8.86. STM3 to words 6 or 7
8.87. STM4 to word 0, 1, 2, 3, or 4
8.88. STM4 to word 5, 6, or 7
8.89. STM5 to word 0, 1, 2, or 3
8.90. STM5 to word 4, 5, 6, or 7
8.91. STM6 to word 0, 1, or 2
8.92. STM6 to word 3, 4, 5, 6, or 7
8.93. STM7 to word 0 or 1
8.94. STM7 to word 2, 3, 4, 5, 6, or 7
8.95. STM8 to word 0
8.96. STM8 to word 1, 2, 3, 4, 5, 6, or 7
8.97. STM9
8.98. STM10
8.99. STM11
8.100. STM12
8.101. STM13
8.102. STM14
8.103. STM15
8.104. STM16
8.105. Half-line write-back
8.106. Full-line write-back
8.107. HSIDEBANDW[3:1] encoding
8.108. HPROTD[4:2] encoding
8.109. HPROTD[1] encoding
8.110. HPROTD[0] encoding
8.111. HSIDEBANDD[3:1] encoding
8.112. Example Peripheral Interface reads and writes
8.113. HPROTP[4:2] encoding
8.114. HPROTP[1] encoding
8.115. AHB-Lite interchangeability
9.1. Clock domains
9.2. AHB clock domain control signals
9.3. Synchronous mode clock enable signals
9.4. Reset modes
11.1. Coprocessor instructions
11.2. Coprocessor control signals
11.3. Pipeline stage update
11.4. Addressing of queue buffers
11.5. Coprocessor instruction retirement conditions
12.1. VIC port signals
13.1. CP14 debug register map
13.2. Terms used in register descriptions
13.3. List of CP14 debug registers
13.4. Debug ID Register bit field definitions
13.5. Results of accesses to the Debug ID Register
13.6. Debug Status and Control Register bit field definitions
13.7. Entry field values, DSCR
13.8. Results of accesses to the Debug Status and Control Register
13.9. Read Data Transfer Register bit field definitions
13.10. Write Data Transfer Register bit field definitions
13.11. Results of accesses to the Data Transfer Registers
13.12. Vector Catch Register bit field definitions
13.13. Results of accesses to the Vector Catch Register
13.14. ARM1136JF-S breakpoint and watchpoint registers
13.15. Breakpoint Value Registers BVR0 to BVR3, bit field definitions
13.16. Breakpoint Value Registers BVR4 and BVR5, bit field definitions
13.17. Results of accesses to the Breakpoint Value Registers
13.18. Breakpoint Control Registers, bit field definitions
13.19. Byte address select field values, bits[8:5], in the BCRs
13.20. Meaning of BCR[21:20] bits in a BCR
13.21. Results of accesses to the Breakpoint Control Registers
13.22. Watchpoint Value Registers, bit field definitions
13.23. Results of accesses to the Watchpoint Value Registers
13.24. Watchpoint Control Registers, bit field definitions
13.25. L/S field values, bits[4:3], in the WCRs
13.26. Interpretation of the L/S field in the WCR for different operations
13.27. Results of accesses to the Watchpoint Control Registers
13.28. CP14 debug instructions
13.29. Debug instruction execution
13.30. Processor behavior on software debug events
13.31. Setting of CP15 registers on debug events
13.32. Values in the link register after exceptions
13.33. Read PC value after Debug state entry
14.1. Supported public instructions
14.2. Scan chain 7 register map
15.1. Instruction interface signals
15.2. ETMIACTL[17:0]
15.3. Data address interface signals
15.4. ETMDACTL[17:0]
15.5. Data value interface signals
15.6. ETMDDCTL[3:0]
15.7. ETMPADV[2:0]
15.8. Coprocessor interface signals
15.9. Other connections
16.1. Definition of cycle timing terms
16.2. Pipeline stages
16.3. Register interlock examples
16.4. Data Processing instruction cycle timing behavior if destination is not PC
16.5. Data processing instruction cycle timing behavior if destination is the PC
16.6. QADD, QDADD, QSUB, and QDSUB instruction cycle timing behavior
16.7. ARMv6 media data processing instructions cycle timing behavior
16.8. ARMv6 sum of absolute differences instruction timing behavior
16.9. Example interlocks
16.10. Example multiply instruction cycle timing behavior
16.11. Branch instruction cycle timing behavior
16.12. Processor state updating instructions cycle timing behavior
16.13. Cycle timing behavior for stores and loads, other than loads to the PC
16.14. Cycle timing behavior for loads to the PC
16.15. <addr_md_1cycle> and <addr_md_2cycle> LDR example instruction
16.16. Load and store double instructions cycle timing behavior
16.17. <addr_md_1cycle> and <addr_md_2cycle> LDRD example instruction
16.18. Load and store multiples, other than load multiples including the PC
16.19. Cycle timing behavior of load multiples, where the PC is in the register list
16.20. RFE and SRS instructions cycle timing behavior
16.21. Synchronization instructions cycle timing behavior
16.22. Coprocessor instructions cycle timing behavior
16.23. SWI, BKPT, Undefined, Prefetch Aborted instructions cycle timing behavior
17.1. AHB-Lite bus interface timing parameters
17.2. Coprocessor port timing parameters
17.3. ETM interface port timing parameters
17.4. Interrupt port timing parameters
17.5. Debug timing parameters
17.6. test port timing parameters
17.7. Static configuration signal port timing parameters
17.8. Reset port timing parameters
A.1. Global signals
A.2. Static configuration signals
A.3. Interrupt signals
A.4. Port signal name suffixes
A.5. Instruction fetch port signals
A.6. Data read port signals
A.7. Data write port signals
A.8. Peripheral port signals
A.9. DMA port signals
A.10. Core to coprocessor signals
A.11. Coprocessor to core signals
A.12. Debug interface signals
A.13. ETM interface signals
A.14. Test signals
C.1. Differences between issue J and issue K

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Figure 14.1 reprinted with permission from IEEE Std. 1149.1-2001, IEEE Standard Test Access Port and Boundary-Scan Architecture, copyright 2001 by IEEE. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.

Confidentiality Status

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision ADecember 2002First Release for r0p0
Revision BFebruary 2003Internal release for r0p1
Revision CFebruary 2003First release for r0p1
Revision DAugust 2003First release for r0p2
Revision E11 May 2004Second release for r0p2
Revision F11 March 2005First release for r1p0.Adds ARMv6k features, see Product revisions on page 1‑57.
Revision G27 July 2005First release for r1p1.System control coprocessor and parts of Debug chapters re-organized.Minor corrections and enhancements.ID information updated to r1p1.
Revision H14 October 2005Second release for r1p1.
Revision I01 December 2006First release for r1p3.No change to technical content.
Revision J06 July 2007First release for r1p5.
Revision K20 February 2009Second release for r1p5.
Copyright © 2002-2007, 2009 ARM Limited. All rights reserved.ARM DDI 0211K
Non-Confidential
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