ARM966E-S ™ TechnicalReference Manual

Revision: r2p1


Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Further reading
Feedback
Feedback on the product
Feedback on this manual
1. Introduction
1.1. About the ARM966E-S processor
1.2. Silicon revision information
2. Programmer’s Model
2.1. About the programmer’s model
2.2. About the ARM9E-S programmer’s model
2.2.1. Data Abort model
2.2.2. ARM966E-S processor abort sources
2.2.3. PLD instruction execution
2.3. CP15 registers
2.3.1. CP15 register map summary
2.3.2. CP15 c0, ID Code Register
2.3.3. CP15 c0, TCM Size Register
2.3.4. CP15 c1, Control Register
2.3.5. CP15 c7, Core Control Register
2.3.6. CP15 c13, Trace Process IdentifierRegister
2.3.7. CP15 c15, Test and Configuration Register
2.3.8. Configuration Control Register
2.3.9. BIST Control Register
3. Memory Map
3.1. About the ARM966E-S memory map
3.2. Tightly-coupled memory address space
3.3. Bufferable write address space
4. Tightly-Coupled Memory Interface
4.1. About the TCM interface
4.2. TCM size
4.3. Enabling TCM
4.3.1. Using INITRAM input pin
4.3.2. Using CP15 c1 Control Register
4.4. TCM write buffers
4.4.1. TCM order bit
4.5. TCM error detection signals
4.6. TCMSEQ signals
4.7. Interface operation
4.7.1. Single-cycle and multicycle accesses
4.7.2. Speculative TCM read access
4.8. TCM implementation examples
4.8.1. Simplest zero-wait-state RAM example
4.8.2. Byte-banks of RAM example
4.8.3. Multiple banks of RAM example
4.8.4. Sequential RAM example
4.8.5. Single or Multiple wait-state RAMexample
4.8.6. Single port RAM example
4.8.7. Dual port DMA-capable RAM example
5. Bus Interface Unit
5.1. About the BIU
5.2. AHB instruction prefetch buffer
5.2.1. Optimized Thumb instruction prefetch
5.2.2. IPB disable bit
5.2.3. AHB error response with IPB
5.2.4. IPB timing examples
5.3. AHB write buffer
5.3.1. Committing write data to the AHB write buffer
5.3.2. Draining write data from the AHB write buffer
5.3.3. Enabling the AHB write buffer
5.3.4. Disabling the AHB write buffer
5.4. AHB bus master interface
5.4.1. Overview of AHB
5.5. AHB transfer descriptions
5.5.1. Back-to-back data transfers
5.5.2. Data burst support
5.6. AHB clocking
5.7. CLK-to-HCLK skew
5.7.1. Clock tree insertion at top level
5.7.2. Hierarchical clock tree insertion
6. Coprocessor Interface
6.1. About the coprocessor interface
6.2. Coprocessor interface signals
6.2.1. Synchronizing the external coprocessor pipeline
6.2.2. External coprocessor clocking
6.2.3. Coprocessor handshake states
6.2.4. Coprocessor handshake encoding
6.2.5. Multiple external coprocessors
6.2.6. Multiple external coprocessor example
6.3. LDC/STC
6.4. MCR/MRC
6.5. Interlocked MCR
6.6. CDP
6.7. Privileged instructions
6.8. Busy-waiting and interrupts
7. Debug Support
7.1. About the debug interface
7.1.1. Stages of debug
7.1.2. Clocks
7.2. Debug systems
7.2.1. The debug host
7.2.2. The protocol converter
7.2.3. ARM966E-S debug target
7.3. ARM966E-S scan chain 15
7.4. Debug interface signals
7.4.1. Entry into debug state on breakpoint
7.4.2. Breakpoints and exceptions
7.4.3. Watchpoints
7.4.4. Watchpoints and exceptions
7.4.5. Debug request
7.4.6. Actions of the ARM9E-S core in debug state
7.5. ARM9E-S core clock domains
7.6. Determining the core and system state
7.7. About the EmbeddedICE-RT
7.8. Disabling EmbeddedICE-RT
7.9. The debug communications channel
7.9.1. Debug Communication Channel Registers
7.9.2. Communications Channel Status Register
7.9.3. Communications Channel Monitor ModeDebug Status register
7.9.4. Communications using the communications channel
7.10. Monitor mode debug
7.11. Debug additional reading
7.11.1. ARM966E-S JTAG TAP ID
8. Embedded Trace Macrocell Interface
8.1. About the ETM interface
8.2. Enabling the ETM interface
8.3. ARM966E-S trace support features
8.3.1. FIFOFULL
8.3.2. Configuration Control Register
8.3.3. Trace Process Identifier Register
9. Test Support
9.1. About the ARM966E-S test methodology
9.2. Scan insertion and ATPG
9.2.1. ARM966E-S test wrapper
9.3. BIST of tightly-coupled memory
9.3.1. BIST algorithm
9.3.2. BIST control register
9.3.3. BIST address and general registers
9.3.4. Running a test
9.3.5. Peek and poke
9.3.6. Pause modes
A. Signal Descriptions
A.1. Signal properties and requirements
A.2. Clock interface signals
A.3. AHB signals
A.4. TCM interface signals
A.4.1. Data TCM interface signals
A.4.2. Instruction TCM interface signals
A.5. Coprocessor interface signals
A.6. Debug signals
A.7. Miscellaneous signals
A.8. ETM interface signals
A.9. Test wrapper signals
B. AC Parameters
B.1. Timing diagrams and timing parameters
B.1.1. Clock, reset, and AHB enable timing
B.1.2. AHB bus master timing
B.1.3. Coprocessor interface timing
B.1.4. Debug interface timing
B.1.5. JTAG interface timing
B.1.6. Exception and configuration timing
B.1.7. AHB bus request and grant-related timing
B.1.8. INTEST wrapper timing
B.1.9. ETM interface timing
B.1.10. TCM interface timing
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. ARM966E-S processor block diagram
2.1. ID Code Register
2.2. TCM Size Register
2.3. Control Register
2.4. Trace Process Identifier Register
2.5. Configuration Control Register
3.1. ARM966E-S memory map
3.2. ITCM aliasing example
4.1. Single-cycle TCM read and write
4.2. Two cycle TCM read and write
4.3. DTCM reads with cancels
4.4. Simplest zero-wait-state RAM example
4.5. Byte-banks of RAM example
4.6. Byte-banks of RAM alternative example
4.7. Multiple banks of RAM example
4.8. Sequential RAM example
4.9. Single or Multiple wait-state RAMexample
4.10. Single port DMA-capable RAM example
4.11. Dual port RAM example
5.1. Nonsequential instruction fetch
5.2. Nonsequential instruction fetch aftera data access
5.3. Back-to-back data transfer writefollowed by read
5.4. Single STM, followed by sequentialinstruction fetch
5.5. Data burst crossing a 1KB boundary
5.6. SWP instruction
5.7. AHB 3:1 clocking example
5.8. ARM966E-S CLK to AHB HCLK sampling
6.1. Pipeline stages
6.2. Connecting multiple coprocessors
6.3. Example handshake logic blocks
6.4. LDC/STC cycle timing
6.5. MCR/MRC transfer timing with busy-wait
6.6. Interlocked MCR/MRC timing with busy-wait
6.7. Late canceled CDP
6.8. Privileged instructions
6.9. Busy-waiting and interrupts
7.1. Clock synchronization
7.2. Typical debug system
7.3. ARM9E-S block diagram
7.4. Breakpoint timing
7.5. Watchpoint entry with data processinginstruction
7.6. Watchpoint entry with branch
7.7. The ARM9E-S, TAP controller, andEmbeddedICE-RT
7.8. Communications Channel Status Register
7.9. Debug Status Register
7.10. TAP ID Register bit order
8.1. ARM966E-S ETM interface
9.1. Test flow for BIST
B.1. Clock, reset and AHB enable timingparameters
B.2. AHB bus master timing parameters
B.3. Coprocessor interface timing parameters
B.4. Debug interface timing parameters
B.5. JTAG interface timing parameters
B.6. Exception and configuration timingparameters
B.7. AHB bus request and grant relatedtiming parameters
B.8. INTEST wrapper timing parameters
B.9. ETM interface timing parameters
B.10. TCM interface timing parameters

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The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM Limited in goodfaith. However, all warranties implied or expressed, including butnot limited to implied warranties of merchantability, or fitnessfor purpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A July2000 First release
Revision B January2002 Second release
Revision C February2002 Third release
Revision D February2002 Fourth release
Revision E February2004 Fifth release r2p1
Copyright © 2000, 2002, 2004 ARM Limited. All rights reserved. ARM DDI 0213E
Non-Confidential