3.3. Bus cycle types

The ARM7EJ-S processor bus interface is pipelined, and so the address class signals, and the memory request signals are broadcast in the bus cycle ahead of the bus cycle to which they refer. This gives the maximum time for a memory cycle to decode the address, and respond to the access request.

A single memory cycle is shown in Figure 3.1.

Figure 3.1. Simple memory cycle

The ARM7EJ-S processor bus interface can perform four different types of memory cycle. These are indicated by the state of the TRANS[1:0] signals. Memory cycle types are encoded on the TRANS[1:0] signals as shown in Table 3.1.

Table 3.1. Cycle types

TRANS[1:0]

Cycle type

Description

b00

I cycle

Internal cycle.

b01

C cycleCoprocessor 15 MCR operation (see MCR operation).

b10

N cycle

Nonsequential cycle.

b11

S cycle

Sequential cycle.

A memory controller for the ARM7EJ-S processor commits to a memory access only on an N cycle or an S cycle.

The ARM7EJ-S processor has three basic types of bus cycle:

Nonsequential cycle

During this cycle, the ARM7EJ-S processor requests a transfer to, or from an address that is unrelated to the address used in the preceding cycle.

Sequential cycle

During this cycle, the ARM7EJ-S processor requests a transfer to or from an address that is either one word or one halfword greater than the address used in the preceding cycle.

Internal cycle

During this cycle, the ARM7EJ-S processor does not require a transfer because it is performing an internal function and no useful prefetching can be performed at the same time.

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