6.6.1. Clocks and synchronization

If the system and test clocks are asynchronous, they must be synchronized externally to the ARM7EJ-S processor. The ARM Multi-ICE debug agent directly supports one or more cores within an ASIC design. Synchronized off-chip debug clocking with the ARM7EJ-S processor requires a three-stage synchronizer. The off-chip device (for example, Multi-ICE) issues a TCK signal, and waits for the RTCK (Returned TCK) signal to be returned. Synchronization is maintained because the off-chip device does not progress to the next TCK until after RTCK is received. Figure 6.5 shows this synchronization.

Figure 6.5. Clock synchronization

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