3.4.3. SIZE[1:0]

The SIZE[1:0] bus encodes the size of the transfer. The processor can transfer word, halfword, and byte quantities. This is encoded on SIZE[1:0] as shown in Table 3.3.

Table 3.3. Transfer widths

SIZE[1:0]

Transfer width

b00

Byte

b01

Halfword

b10

Word

b11

Reserved

The size of transfer does not change during a burst of S cycles.

Note

A writable memory system for the ARM7EJ-S processor must have individual byte write enables. Both the C Compiler and the ARM debug tool chain (for example, Multi-ICE) assume that arbitrary bytes in the memory can be written. If individual byte write capability is not provided, it might not be possible to use either of these tools.

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