B.7.3. Jazelle state breakpoints and watchpoints

On entry to debug from Jazelle the PC contains the address of the instruction not executed because of debug entry plus four bytes (except for software breakpoints where PC equals address of breakpoint instruction plus four bytes). The PC is then frozen until the core state is forced to ARM state. This behavior means that whatever the cause of debug entry from Jazelle state the return address is always the PC value at entry minus four bytes.

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