3.2. Bus interface signals

The signals in the ARM7EJ-S processor bus interface can be grouped into four categories:

The clocking and clock control signals are:

The address class signals are:

The memory request signals are:

The data timed signals are:

Each of these signal groups shares a common timing relationship to the bus interface cycle. All signals in the ARM7EJ-S processor bus interface are generated on or sampled at the rising edge of CLK.

Bus cycles can be extended using the CLKEN signal (see Using CLKEN to control bus cycles). All other sections of this chapter describe a simple system in which CLKEN is permanently HIGH.

Copyright ©  2001 ARM Limited. All rights reserved.ARM DDI 0214B
Non-Confidential