| Copyright © 2001 ARM Limited. All rights reserved. | ARM DDI 0214B |
| Non-Confidential | |
 PDF version | |
| Home > Debug Interface and EmbeddedICE-RT > Using Watchpoints and breakpoints in Jazelle state > Monitor mode |
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| Home > Debug Interface and EmbeddedICE-RT > Using Watchpoints and breakpoints in Jazelle state > Monitor mode | |||
In monitor mode debug:
Execute
the LDR/STR instruction and then take
a Data Abort. The link register is the PC value of the last instruction
not to execute + 4. This enables the following return command to
be used, as in ARM state:
SUBS pc, lr, #4
Cause Prefetch Aborts. The link register is calculated in the same way as normal Prefetch Aborts. The return instruction remains:
SUBS pc, lr, #4
| Copyright © 2001 ARM Limited. All rights reserved. | ARM DDI 0214B |
| Non-Confidential | |
| PDF version | |
| Home > Debug Interface and EmbeddedICE-RT > Using Watchpoints and breakpoints in Jazelle state > Monitor mode |