6.5.1. Entry into debug state on breakpoint

An instruction being fetched from memory is sampled at the end of a cycle. To apply a breakpoint to that instruction, the breakpoint signal must be asserted by the end of the same cycle. This is shown in Figure 6.4.

Figure 6.4. Breakpoint timing

You can build external logic, such as additional breakpoint comparators, to extend the breakpoint functionality of the EmbeddedICE-RT logic. You must apply their output to the DBGEBKPT input.


The timing of the DBGEBKPT input makes it unlikely that data-dependent external breakpoints are possible. DBGEBKPT is not supported in Jazelle state, and must not be asserted while the core is in Jazelle state.

A breakpointed instruction is allowed to enter the Execute stage of the pipeline, but any state change as a result of the instruction is prevented. All instructions prior to the breakpointed instruction complete as normal.


If a breakpointed instruction does not reach the Execute stage, for instance, if an earlier instruction is a branch, then both the breakpointed instruction and breakpoint status are discarded and the ARM does not enter debug state.

In Figure 6.4 the third instruction breakpointed. The debug entry sequence is initiated when this instruction enters the Execute stage. The processor completes the debug entry sequence and asserts DBGACK two cycles later.

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