ETMBIGEND | Output | Big-endian configuration indication for the
ETM. |
| ETMCHSD[1:0] | Output | Coprocessor handshake decode indication for
the ETM. |
| ETMCHSE[1:0] | Output | Coprocessor handshake execute indication for
the ETM. |
ETMCLKEN | Output | ETM clock enable. |
| ETMDA[31:0] | Output | Data address for the ETM. |
| ETMDABORT | Output | Data abort for the ETM. |
| ETMDBGACK | Output | Debug state indication for the ETM. |
| ETMDMAS[1:0] | Output | Data memory access size indication for the
ETM. |
| ETMDnMREQ | Output | Data memory request for the ETM. |
| ETMDnRW | Output | Data read and write indication for the ETM. |
| ETMDSEQ | Output | Sequential data access indication for the ETM. |
ETMHIVECS | Output | Exception vectors configuration indication
for the ETM. |
| ETMIA[31:0] | Output | Instruction address for the ETM. |
| ETMID15TO11[15:11] | Output | Instruction data field for the ETM. |
| ETMID31TO25[31:25] | Output | Instruction data field for the ETM. |
| ETMIJBIT | Output | Jazelle state indication for the ETM. |
| ETMInMREQ | Output | Sequence pipeline follower. If LOW at the end
the cycle, then the processor requires an ETM memory access during
the following cycle. |
| ETMINSTREXEC | Output | Instruction execute indication for the ETM. |
| ETMINSTRVALID | Output | Instruction valid indication for the ETM. |
| ETMISEQ | Output | Sequential instruction access for the ETM. |
| ETMITBIT | Output | Thumb state indication for the ETM. |
| ETMLATECANCEL | Output | Coprocessor late cancel indication for the
ETM. |
| ETMPASS | Output | Coprocessor instruction execute indication
for the ETM. |
| ETMPROCID[31:0] | Output | Process ID for the ETM. |
| ETMPROCIDWR | Output | Process ID Write indication for the ETM. |
ETMPWRDOWN | Input | This signal must be tied HIGH if an ETM is
not present in the design. |
| ETMRDATA[31:0] | Output | Read data for the ETM. |
| ETMRNGOUT[1:0] | Output | Watchpoint register match indication for the
ETM. |
| ETMWDATA[31:0] | Output | Write data for the ETM. |
| ETMZIFIRST | Output | Indicates the current ARM instruction is the
first being traced for the current Jazelle instruction. |
| ETMZILAST | Output | Indicates the current ARM instruction is the
last being traced for the current Jazelle instruction. |
| TRACEPROCID[31:0] | Input | Trace Process ID. This signal comes from a
CP15, is registered, and then exported as ETMPROCID[31:0]. |
| TRACEPROCIDWR | Input | Trace Process ID Write. This signal is asserted
when TRACEPROCID[31:0] is active. |
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