5.3. Handshake signals CHSD and CHSE

The handshake signals CHSD (decode stage of the pipeline) and CHSE (execute stage) are used by the coprocessor to indicate if it can handle the current instruction.

Table 5-1 describes how the handshake signals CHSD[1:0] and CHSE[1:0] are encoded.

Table 5.1. Handshake signals

StateCHSD/CHSEDescription
ABSENTb10

If there is no coprocessor attached that can execute the coprocessor instruction, the handshake signals indicate the ABSENT state. In this case, the ARM7EJ-S processor takes the undefined instruction trap.

WAITb00

If there is a coprocessor attached that can handle the instruction, but not immediately, the coprocessor handshake signals are driven to indicate that the ARM7EJ-S processor must stall until the coprocessor can catch up. This is known as the busy-wait condition. In this case, the ARM7EJ-S processor loops in an idle state waiting for CHSE[1:0] to be driven to another state, or for an interrupt to occur. If CHSE[1:0] changes to ABSENT, the undefined instruction trap is taken. If CHSE[1:0] changes to GO or LAST, the instruction proceeds as follows. If an interrupt occurs, the ARM7EJ-S processor is forced out of the busy-wait state. This is indicated to the coprocessor by the CPPASS signal going LOW. The instruction is restarted later and so the coprocessor must not commit to the instruction (it must not change the coprocessor state) until it has seen CPPASS HIGH, when the handshake signals indicate the GO or LAST condition.

GOb01

The GO state indicates that the coprocessor can execute the instruction immediately, and that it requires another cycle of execution. Both the ARM7EJ-S processor and the coprocessor must also consider the state of the CPPASS signal before actually committing to the instruction. For an LDC or STC instruction, the coprocessor instruction drives the handshake signals with GO when two or more words still have to be transferred.

When only one further word is to be transferred, the coprocessor drives the handshake signals with LAST. During the Execute stage, the ARM7EJ-S processor outputs the address for the LDC or STC. At this stage, the ARM7EJ-S processor also has to perform a data request corresponding to the LDC or STC to be performed. Figure 5.1 and Figure 5.2 show examples of these operations.

LASTb11An LDC or STC can be used for more than one item of data. If this is the case, possibly after busy waiting, the coprocessor drives the coprocessor handshake signals with a number of GO states, and in the penultimate cycle drives LAST (indicating that the next transfer is the final one). If there is only one transfer, the sequence is [WAIT,[WAIT,...]],LAST.
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