1.4.3. Thumb instruction set summary

The Thumb instruction set summary is shown in Table 1.7.

Table 1.7. Thumb instruction set summary

MoveImmediateMOV Rd, #8bit_Imm
 High to LowMOV Rd, Hs
 Low to HighMOV Hd, Rs
 High to HighMOV Hd, Hs
ArithmeticAddADD Rd, Rs, #3bit_Imm
 Add Low and LowADD Rd, Rs, Rn
 Add High to LowADD Rd, Hs
 Add Low to HighADD Hd, Rs
 Add High to HighADD Hd, Hs
 Add ImmediateADD Rd, #8bit_Imm
 Add Value to SPADD SP, #7bit_Imm ADD SP, #-7bit_Imm
 Add with carryADC Rd, Rs
 SubtractSUB Rd, Rs, Rn SUB Rd, Rs, #3bit_Imm
 Subtract ImmediateSUB Rd, #8bit_Imm
 Subtract with carrySBC Rd, Rs
 NegateNEG Rd, Rs
 MultiplyMUL Rd, Rs
 Compare Low and LowCMP Rd, Rs
 Compare Low and HighCMP Rd, Hs
 Compare High and LowCMP Hd, Rs
 Compare High and HighCMP Hd, Hs
 Compare NegativeCMN Rd, Rs
 Compare ImmediateCMP Rd, #8bit_Imm
LogicalANDAND Rd, Rs
 Bit clearBIC Rd, Rs
 Move NOTMVN Rd, Rs
 Test bitsTST Rd, Rs
Shift/RotateLogical shift leftLSL Rd, Rs, #5bit_shift_imm LSL Rd, Rs
 Logical shift rightLSR Rd, Rs, #5bit_shift_imm LSR Rd, Rs
 Arithmetic shift rightASR Rd, Rs, #5bit_shift_imm ASR Rd, Rs
 Rotate rightROR Rd, Rs
 If Z setBEQ label
 If Z clearBNE label
 If C setBCS label
 If C clear BCC label
 If N setBMI label
 If N clear BPL label
 If V setBVS label
 If V clear BVC label
 If C set and Z clearBHI label
 If C clear or Z setBLS label

If N set and V set, or

If N clear and V clear

BGE label

If N set and V clear, or

If N clear and V set

BLT label

If Z clear, and N and V set, or

If Z clear, and N and V clear

BGT label

If Z set, or

N set and V clear, or

N clear and V set

BLE label
 UnconditionalB label
 Long branch with linkBL label

Long branch, link and

exchange instruction

BLX label
Branch and exchangeTo address held in Low regBX Rs
 To address held in High regBX Hs
Branch, link, and exchangeTo address held in Low regBLX Rs
 To address held in High regBLX Hs
LoadWith immediate offset-
  • Word

LDR Rd, [Rb, #7bit_offset]
  • Halfword

LDRH Rd, [Rb, #6bit_offset]
  • Byte

LDRB Rd, [Rb, #5bit_offset]
 With register offset-
  • Word

LDR Rd, [Rb, Ro]
  • Halfword

LDRH Rd, [Rb, Ro]
  • Halfword signed

LDRSH Rd, [Rb, Ro]
  • Byte

LDRB Rd, [Rb, Ro]
  • Byte signed

LDRSB Rd, [Rb, Ro]
 PC-relativeLDR Rd, [PC, #10bit_Offset]
 SP-relativeLDR Rd, [SP, #10bit_Offset]
  • Using PC

ADD Rd, PC, #10bit_Offset
  • Using SP

ADD Rd, SP, #10bit_Offset
 MultipleLDMIA Rb!, <reglist>
StoreWith immediate offset-
  • Word

STR Rd, [Rb, #7bit_offset]
  • Halfword

STRH Rd, [Rb, #6bit_offset]
  • Byte

STRB Rd, [Rb, #5bit_offset]
 With register offset-
  • Word

STR Rd, [Rb, Ro]
  • Halfword

STRH Rd, [Rb, Ro]
  • Byte

STRB Rd, [Rb, Ro]
 SP-relativeSTR Rd, [SP, #10bit_offset]
 MultipleSTMIA Rb!, <reglist>
Push/PopPush registers onto stackPUSH <reglist>
 Push LR and registers onto stackPUSH <reglist, LR>
 Pop registers from stackPOP <reglist>
 Pop registers and PC from stackPOP <reglist, PC>
Software interrupt-SWI 8bit_Imm
Software breakpoint-BKPT<immediate>
Copyright ©  2001 ARM Limited. All rights reserved.ARM DDI 0214B