5.9. MCRR operation

MCRR operations are very similar to MCR operations, as shown in Figure 5.6. The only difference is that the coprocessor has to remain in the Execute stage for at least two cycles, one for each of the registers to be transferred.

The coprocessor sends a GO onto CHSD during the Decode stage of the coprocessor pipeline (corresponding to the first register to be transferred, cycle 4 on the figure), then a LAST onto CHSE for the second register (cycle 5).

Figure 5.6. MCRR cycle timing

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