5.13. Busy-waiting and interrupts

The coprocessor is permitted to stall or busy-wait the ARM7EJ-S processor during the execution of a coprocessor instruction if, for example, it is still busy with an earlier coprocessor instruction. To do this, the coprocessor associated with the Decode stage instruction drives WAIT onto CHSD[1:0]. When the instruction concerned enters the Execute stage of the pipeline the coprocessor can drive WAIT onto CHSE[1:0] for as many cycles as necessary to keep the instruction in the busy-wait loop.For interrupt latency reasons, the coprocessor can be interrupted while busy-waiting, and cause the current instruction to be abandoned. Abandoning execution is done through CPPASS. The coprocessor must monitor the state of CPPASS during every busy-wait cycle:

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