5.6. MCR operation

An MCR operation is similar to an LDC operation, except that the ARM7EJ-S processor does not have to perform a memory access. This saves one cycle compared with the LDC operation. A timing diagram is shown in Figure 5.3.

The case of an MCR operation to coprocessor 15 is described in Coprocessor 15 MCR operation.

Figure 5.3. MCR cycle timing

Note

In Figure 5.3, as for an LDC operation, the coprocessor still has to sample the CPDOUT bus at the end of the write pipeline stage.

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