1.3. ARM7EJ-S processor block, core, and interface diagrams

The ARM7EJ-S processor architecture, core, and interface diagrams are shown in the following figures:

Figure 1.3. Block diagram

Refer to Chapter 6 Debug Interface and EmbeddedICE-RT for a description of the EmbeddedICE-RT logic.

Figure 1.4. Core block diagram

Figure 1.5. Interface diagram

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