ARM7EJ-S Technical Reference Manual Appendix B. Debug in Depth

Appendix B. Debug in Depth

This appendix describes in further detail the debug features of the ARM7EJ-S processor, and includes additional information about the EmbeddedICE-RT logic. It contains the following sections:

Scan chains and JTAG interface
Resetting the TAP controller
Instruction register
Public instructions
Test data registers
Determining the core and system state
Behavior of the program counter during debug
Priorities and exceptions
EmbeddedICE-RT logic
Vector catching
Coupling breakpoints and watchpoints
Disabling EmbeddedICE-RT
EmbeddedICE-RT timing.

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