B.9. EmbeddedICE-RT logic

The EmbeddedICE-RT logic is integral to the ARM7EJ-S processor. It has two hardware breakpoint or watchpoint units, each of which can be configured to monitor either the instruction memory interface or the data memory interface. Each watchpoint unit has registers that set the address, data, and control fields for both values and masks. The registers used are shown in Table B.4.

When debugging, the ARM7EJ-S processor differentiates between the instruction and data flows. Therefore, you must specify if the watchpoint unit refers to instruction or data accesses by using bit 3 of the control value register:

Bit 3 of the control mask register is always clear and cannot be set. Bit 3 also determines whether the internal IBREAKPT or DWPT signal must be driven by the result of the comparison. Figure B.6 gives an overview of the operation of the EmbeddedICE-RT logic.

The general arrangement of the EmbeddedICE-RT logic is shown in Figure B.6.

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