9.18. Software interrupt, undefined instruction, and exception entry

Exceptions, software interrupts (SWIs), and undefined instructions force the PC to a specific value and refill the instruction pipeline from that address, as follows:

  1. During the first cycle, the ARM7EJ-S processor constructs the forced address, and a mode change might take place.

  2. During the second cycle:

    1. The ARM7EJ-S processor performs a fetch from the exception address.

    2. The return address to be stored in r14 is calculated.

    3. The state of the CPSR is saved in the relevant SPSR.

  3. During the third cycle, the ARM7EJ-S processor performs a fetch from the exception address + 4, refilling the instruction pipeline.

The exception entry cycle timings are show in Table 9.25, where:

pc

Is one of:

  • the address of the SWI instruction for SWIs

  • the address of the instruction following the last one to be executed before entering the exception for interrupts

  • the address of the aborted instruction for Prefetch Aborts

  • the address of the instruction following the one that attempted the aborted data transfer for Data Aborts.

Xn

Is the appropriate exception address.

Table 9.25. Exception entry cycle timings

CycleADDRRDATATRANSCPTBIT
1Xn N cycle0
2Xn+4(Xn)S cycle0
3Xn+8(Xn+4)S cycle0
  (Xn+8)  

Note

The value on the RDATA bus can be unpredictable in the case of Prefetch Abort or Data Abort entry.

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