9.6. Data operations

A normal data operation executes in a single execute cycle except where the shift is determined by the contents of a register. A normal data operation requires up to two operands, that are read from the register file onto the A and B buses.

The ALU combines the A bus operand with the (shifted) B bus operand according to the operation specified in the instruction. The ARM7EJ-S processor pipelines this result and writes it into the destination register, when required. Compare and test operations do not write a result as they only affect the status flags.

An instruction prefetch occurs at the same time as the data operation, and the PC is incremented.

When a register-specified shift is used, an additional execute cycle is needed to read the shifting register operand. The instruction prefetch occurs during this first cycle.

The PC can be one or more of the register operands. When the PC is the destination, the external bus activity is affected. When the ARM7EJ-S processor writes the result to the PC, the contents of the instruction pipeline are invalidated, and the ARM7EJ-S processor takes the address for the next instruction prefetch from the ALU rather than the incremented address. The ARM7EJ-S processor refills the instruction pipeline before any further instruction execution takes place. Exceptions are locked out while the pipeline is refilling.


Shifted register with destination equal to PC is not possible in Thumb state.

Table 9.7 shows the data operation cycle timings.

Table 9.7. Cycle timings for data operations

Normal1pc+3i(pc+2i)S cycle
ADD, SUB, RSB, ADC, SBC, RSC, MOV operation, dest=pc1pc'(pc+2i)N cycle
 2pc'+ i(pc')S cycle
 3pc'+2i(pc'+i)S cycle
   (pc'+ 2i) 
shift(Rs)1pc+3i(pc+2i)I cycle
 2pc+3i-S cycle
shift or AND, ORR, EOR, MVN operation, dest=pc1pc+3i(pc+2i)I cycle
 2pc'-N cycle
 3pc'+i(pc')S cycle
 4pc'+2i(pc'+i)S cycle
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