4.3. Maximum interrupt latency

The processor samples the interrupt input pins on the rising-edge of the system clock, CLK, with CLKEN HIGH. The sampled signal is examined and can cause an interrupt in the following cases:

If the sampled signal is asserted at the same time as a multi-cycle instruction has started its second or subsequent cycle of execution, the interrupt exception entry does not start until the instruction has completed. The worst-case interrupt latency occurs when the longest possible LDM instruction incurs a Data Abort. The processor must enter the Data Abort mode before taking the interrupt so that the interrupt exception exit can occur correctly. This causes a worst-case latency of 24 cycles:

Note

The worst-case latency for IRQs can be longer, at least as long as the worst-case FIQ service routine.

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