9.3. Thumb branch with link

A Thumb Branch with Link (BL) operation comprises two consecutive Thumb instructions, and takes four cycles as follows:

  1. The first instruction acts as a simple data operation. The ARM7EJ-S processor takes a single cycle to add the PC to the upper part of the offset and store the result in r14. If the previous instruction requested a data memory access, the data is transferred in this cycle.

  2. The second instruction acts similarly to the ARM BL instruction over three cycles:

    1. During the first cycle, the ARM7EJ-S processor calculates the final branch target address while performing a prefetch from the current PC.

    2. During the second cycle, the ARM7EJ-S processor performs a fetch from the branch destination, while calculating the return address to be stored in r14.

    3. During the third cycle, the ARM7EJ-S processor performs a fetch from the destination + 2, refilling the instruction pipeline.

Table 9.4 shows the cycle timings of the complete operation.

Table 9.4. Cycle timings for Thumb branch with link

CycleADDRRDATATRANS
1pc+3i(pc+i)S cycle
2pc'(pc+3i)N cycle
3pc'+i(pc')S cycle
4pc'+i(pc'+i)S cycle
  (pc'+i) 
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