1.4.1. Format summary

This section provides a summary of the ARM and Thumb instruction sets.

A key to the ARM and Thumb instruction set tables is shown in Table 1.1.

The ARM7EJ-S processor uses an implementation of the ARMv5TE with ARM Jazelle technology (ARMv5TEJ). For a description of the ARM Thumb refer to the ARM Architecture Reference Manual. For a description of the Jazelle technology, refer to http://java.sun.com.

Table 1.1. Key to instruction set tables

SymbolDescription
{cond}See Table 1.6.
<Oprnd2>See Table 1.4.
{field}See Table 1.5.
SSets condition codes (optional).
BByte operation (optional).
HHalfword operation (optional).
TForces address translation. Cannot be used with pre-indexed addresses.
Addressing modesSee Table 1.3.
#32bit_ImmA 32-bit constant, formed by right-rotating an 8-bit value by an even number of bits.
<reglist>A comma-separated list of registers, enclosed in braces ({ and }).
xSelects HIGH or LOW 16 bits of register Rm. T selects the HIGH 16 bits. (T = top) B selects the LOW 16 bits. (B = bottom).
ySelects HIGH or LOW 16 bits of register Rs. T selects the HIGH 16 bits. (T = top) B selects the LOW 16 bits. (B = bottom).
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