9.14. Store multiple registers

Store multiple (STM) instructions proceed in a similar way to load multiple instructions:

  1. During the first cycle, the ARM7EJ-S processor calculates the address of the first word to be transferred, while performing an instruction prefetch and also calculating the new value for the base register.

  2. During the second and subsequent cycles, ARM7EJ-S processor stores the data requested in the previous cycle and calculates the address of the next word to be transferred.

When a Data Abort occurs, the instruction continues to completion. The ARM7EJ-S processor restores the modified base pointer (which the load activity before the abort occurred might have overwritten).

Table 9.23 shows the STM cycle timings.

Table 9.23. Cycle timings for STM

1 register1da(pc+2i)N cycle 
 2pc+3i-N cycleR
   (pc+3i) -
n registers (n > 1)1da(pc+2i)N cycle 
 2da++-S cycleR
 .da++-S cycleR'
 nda++ S cycleR''
 n+1pc+3i-N cycleR'''
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