4.2.3. Re-enabling interrupts after an interrupt exception

You must take care when re-enabling interrupts (for example at the end of an interrupt routine or with a re-entrant interrupt handler). You must ensure that the original source of the interrupt has been removed before interrupts are enabled again on the processor. If you cannot guarantee this, the processor might retake the interrupt exception prematurely.When considering the timing relation of removing the source of interrupt and re-enabling interrupts on the processor, you must take into account the pipelined nature of the processor and the memory system to which it is connected. For example, the instruction that clears the interrupt request (that is, deassertion of nFIQ or nIRQ) typically does not take effect until after the instruction reaches the Memory pipeline stage. The instruction that re-enables interrupts on the processor can cause the processor to be sensitive to interrupts as early as when the instruction reaches the Execute pipeline stage.For example, consider the following instruction sequence:

STR r0, [r1] ;Write to interrupt controller, clearing interruptSUBS pc, r14, #4 ;Return from interrupt routine

The execution of this code sequence is illustrated in Figure 4.1.

Figure 4.1. Retaking the FIQ exception

In Figure 4.1, the STR to the interrupt controller does not cause the deassertion of the nFIQ input until cycle 4. The SUBS instruction causes the processor to be sensitive to interrupts during cycle 3. Because of this timing relationship, the processor retakes the FIQ exception in this example.

The FIQDIS (and similarly IRQDIS) output from the processor indicates when the processor is sensitive to the state of nFIQ (nIRQ) (LOW for sensitive, HIGH for insensitive). If nFIQ is asserted in the same cycle that FIQDIS is LOW, the processor takes the FIQ exception in a later cycle, even if the nFIQ input is subsequently deasserted.

There are several approaches that you can adopt to ensure that interrupts are not enabled too early on the processor. The best approach to use is highly dependent on the overall system, and can be a combination of hardware and software. Example approaches are to:

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