9.21. Store coprocessor register (to memory)

The store coprocessor (STC) operation transfers one or more words of data from a coprocessor to memory.

The coprocessor commits to the transfer only when it is ready to write the data. The coprocessor indicates that it is ready for the transfer to commence by driving CHSD or CHSE to GO. The ARM7EJ-S processor produces addresses and requests data memory writes on behalf of the coprocessor, which is expected to produce the data at sequential rates.

The coprocessor is responsible for determining the number of words to be transferred. It indicates this by setting CHSD or CHSE to LAST in the cycle before it is ready to initiate the transfer of the last data word.

An interrupt can cause the ARM7EJ-S processor to abandon a busy-waiting coprocessor instruction (see Busy-waiting and interrupts).

Note

Coprocessor operations are only available in ARM state.

The store coprocessor register cycle timings are shown in Table 9.28, where:

INSTR

Indicates the signal CPINSTR.

IN

Indicates the signal CPDIN.

P

Indicates the signal CPPASS.

LC

Indicates the signal CPLATECANCEL.

D

Indicates the signal CHSD.

E

Indicates the signal CHSE.

Table 9.28. Cycle timings for STC

CycleADDRRDATATRANSWDATAINSTRINPLCDE
1 register, ready   (pc)     
 1pc+3i(pc+2i)I cycle (pc+i) 00LAST-
 2da-I cycle (pc+2i) 10 -
 3da-S cycle (pc+2i)CPdata100 -
 4pc+3i-N cycleCPdata1(pc+2i) 00 -
   (pc+3i)  (pc+2i)     
1 register, not ready   (pc)     
 1pc+3i(pc+2i)I cycle (pc+i) 00WAIT 
 .pc+3i-I cycle (pc+2i) 10 WAIT
 n+1da-I cycle (pc+2i) 10 LAST
 n+2da-I cycle (pc+2i) 10 -
 n+3da-S cycle (pc+2i)CPdata100 -
 n+4pc+3i-N cycleCPdata1(pc+2i) 00 -
   (pc+3i)  (pc+2i)     
m registers (m > 1), ready   (pc)     
 1pc+3i(pc+2i)I cycle (pc+i) 00GO 
 2da-I cycle (pc+2i) 10 GO
 3da-S cycle (pc+2i)data(1)10 GO
 4da++-S cycledata(1)(pc+2i)data(2)10 GO
 .da++-S cycledata(m-4)(pc+2i)data(m-3)10 GO
 mda++-S cycledata(m-3)(pc+2i)data(m-2)10 LAST
 m+1da++-S cycledata(m-2)(pc+2i)data(m-1)10 -
 m+2da++-S cycledata(m-1)(pc+2i)data(m)00 -
 m+3pc+3i-N cycledata(m)(pc+2i) 00 -
   (pc+3i)  (pc+2i)     
m registers, (m > 1), not ready  (pc)     
 1pc+3i(pc+2i)I cycle (pc+i) 00WAIT 
 .pc+3i-I cycle (pc+2i) 10 WAIT
 n+1da-I cycle (pc+2i) 10 GO
 n+2da-I cycle (pc+2i) 10 GO
 n+3da-S cycle (pc+2i)data(1)10 GO
 n+4da++-S cycledata(1)(pc+2i)data(2)10 GO
 .da++-S cycledata(2)(pc+2i)data(m-3)10 GO
 n+mda++-S cycledata(m-3)(pc+2i)data(m-2)10 LAST
 n+m+1da++-S cycledata(m-2)(pc+2i)data(m-1)10 -
 n+m+2da++-S cycledata(m-1)(pc+2i)data(m)00 -
 n+m+3pc+3i-N cycledata(m)(pc+2i) 00 -
   (pc+3i)  (pc+2i)     
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