8.1. About device reset

This section describes the ARM7EJ-S processor reset signals and how you must use them for correct operation of the device.

The ARM7EJ-S processor has two reset inputs:


This is the main processor reset that initializes the majority of the core logic.


This the debug logic reset that you can use to reset the TAP controller and the EmbeddedICE-RT unit.

Both nRESET and DBGnTRST are active LOW signals that asynchronously reset logic in the core. You must take care, when designing the logic, to drive these reset signals correctly.

Copyright ©  2001 ARM Limited. All rights reserved.ARM DDI 0214B