9.22. Coprocessor register transfer (to ARM)

The move from coprocessor (MRC) operation transfers a single coprocessor register into the specified ARM register.

An interrupt can cause the ARM7EJ-S processor to abandon a busy-waiting coprocessor instruction (see Busy-waiting and interrupts).

Note

Coprocessor operations are only available in ARM state.

The MRC instruction cycle timings are shown in Table 9.29, where:

P

Indicates the signal CPPASS.

LC

Indicates the signal CPLATECANCEL.

Table 9.29. Cycle timings for MRC

CycleADDRRDATATRANSCPINSTRCPDINP LC CHSDCHSE
Ready    (pc)     
 1pc+3i(pc+2i)I cycle(pc+i) 00LAST 
 2pc+3i-S cycle(pc+2i) 10 -
   (pc+3i) (pc+2i)CPdata    
Not ready    (pc)     
 1pc+3i(pc+2i)I cycle(pc+i) 00WAIT 
 .pc+3i-I cycle(pc+2i) 10 WAIT
 n+1pc+3i-I cycle(pc+2i) 10 LAST
 n+2pc+3i-S cycle(pc+2i) 10 -
   (pc+3i) (pc+2i)CPdata    
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