9.20. Load coprocessor register (from memory)

The load coprocessor (LDC) operation transfers one or more words of data from memory to a coprocessor.

The coprocessor commits to the transfer only when it is ready to accept the data. The coprocessor indicates that it is ready for the transfer to commence by driving CHSD or CHSE to GO. The ARM7EJ-S processor produces addresses and requests data memory reads on behalf of the coprocessor, which is expected to accept the data at sequential rates.

The coprocessor is responsible for determining the number of words to be transferred. It indicates this by setting CHSD or CHSE to LAST in the cycle before it is ready to initiate the transfer of the last data word.

An interrupt can cause the ARM7EJ-S processor to abandon a busy-waiting coprocessor instruction (see Busy-waiting and interrupts).

Note

Coprocessor operations are only available in ARM state.

The load coprocessor register cycle timings are shown in Table 9.27, where:

INSTR

Indicates the signal CPINSTR.

OUT

Indicates the signal CPDOUT.

P

Indicates the signal CPPASS.

LC

Indicates the signal CPLATECANCEL.

D

Indicates the signal CHSD.

E

Indicates the signal CHSE.

N

Indicates the signal CLKEN.

Table 9.27. Cycle timings for load coprocessor register operations

CycleADDRRDATATRANSINSTROUTP LCDEN
1 register, ready  (pc)     1
 1pc+3i(pc+2i)I cycle(pc+i) 00LAST 1
 2da-N cycle(pc+2i) 10 -1
 3pc+3i(da)N cycle(pc+2i) 00 -1
   (pc+3i) (pc+2i)     0
     (pc+3i)(da)    1
1 register, not ready  (pc)      
 1pc+3i(pc+2i)I cycle(pc+i) 00WAIT 1
  pc+3i-I cycle(pc+2i) 10 WAIT1
 n+1pc+3i-I cycle(pc+2i) 10 LAST1
 n+2da-N cycle(pc+2i) 10 -1
 n+3pc+3i(da)N cycle(pc+2i) 00 -1
   (pc+3i) (pc+2i)     0
     (pc+3i)(da)    1
m registers (m > 1) ready (pc)      
 1pc+3i(pc+2i)I cycle(pc+i) 00GO 1
 2da-N cycle(pc+2i) 10 GO1
 3da++(da)S cycle(pc+2i) 10 GO1
  da++(da++)S cycle(pc+2i)(da)10 GO1
 mda++(da++)S cycle(pc+2i)(da++)10 LAST1
 m+1da++(da++)S cycle(pc+2i)(da++)10 -1
 m+2pc+3i(da++)N cycle(pc+2i)(da++)00 -1
   (pc+3i) (pc+2i)     0
     (pc+3i)(da++)    1
m registers (m > 1) not ready (pc)      
 1pc+3i(pc+2i)I cycle(pc+i) 00WAIT 1
  pc+3i-I cycle(pc+2i) 10 WAIT1
 n+1pc+3i-I cycle(pc+2i) 10 GO1
 n+2da-N cycle(pc+2i) 10 GO1
 n+3da++(da)S cycle(pc+2i) 10 GO1
  da++(da++)S cycle(pc+2i)(da)10 GO1
 n+mda++(da++)S cycle(pc+2i)(da++)10 LAST1
 n+m+1da++(da++)N cycle(pc+2i)(da++)10 -1
 n+m+2pc+3i(da++)N cycle(pc+2i)(da++)00 -1
   (pc+3i) (pc+2i)     0
     (pc+3i)(da++)    1
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