9.4. Branch and Exchange

Branch and Exchange operations comprise the following:

Execution of these instructions takes three cycles, and is similar to a branch, as follows:

  1. During the first cycle, the ARM7EJ-S processor extracts the branch destination and the new core state while performing a prefetch from the current PC. This prefetch is performed in all cases, because by the time the decision to take the branch has been reached, it is already too late to prevent the prefetch. In the case of BX and BLX <Rm>, the branch destination new state comes from the register. For BLX <immediate> the destination is calculated as a PC offset. The state is always changed.

    If the previous instruction requested a memory access (and there is no interlock in the case of BX or BLX <register>), the data is transferred in this cycle.

  2. During the second cycle, the ARM7EJ-S processor performs a fetch from the branch destination, using the new instruction width, dependent on the state that has been selected. If the link bit is set, the return address to be stored in r14 is calculated.

  3. During the third cycle, the ARM7EJ-S processor performs a fetch from the destination +2 or +4 dependent on the new specified state, refilling the instruction pipeline.

Table 9.5 shows the cycle timings, where:

i

Is the instruction width before the BX or BLX instruction.

i'

Is the instruction width after the BX or BLX instruction.

tj'

Is the state of the CPTBIT and CPJBIT signals after the BX or BLX instruction.

Table 9.5. Cycle timings for Branch and Exchange

CycleADDRRDATATRANSCPTBIT, CPJBIT
1pc'(pc+2i)N cycletj'
2pc'+i'(pc')S cycletj'
3pc'+2i'(pc'+i')S cycletj'
  (pc'+2i')  
Copyright ©  2001 ARM Limited. All rights reserved.ARM DDI 0214B
Non-Confidential