2.8.3. The J bit

The J bit in the CPSR indicates when the ARM7EJ-S processor is in Jazelle state.

When:

J = 0

The processor is in ARM or Thumb state, depending on the T bit.

J = 1

The processor is in Jazelle state.

Note

  • The combination of J = 1 and T = 1 causes similar effects to setting T=1 on a non Thumb-aware processor. That is, the next instruction executed causes entry to the Undefined Instruction exception. Entry to the exception handler causes the processor to re-enter ARM state, and the handler can detect that this was the cause of the exception because J and T are both set in SPSR_und.

  • MSR cannot be used to change the J bit in the CPSR.

  • The placement of the J bit avoids any usage of the status or extension bytes in code run on ARMv5TE or earlier processors. This ensures that OS code written using the older CPSR, SPSR, CPSR_all, or SPSR_all syntax for the destination of an MSR instruction continues to work.

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