9.12. Store register

A store register operation takes two or more cycles. Duringthe last Execute cycle, the store address is calculated, and the data to be stored is read onto the C bus.

Table 9.21 shows the cycle timing for a store register operation.

Table 9.21. Cycle timings for a store register operation

CycleADDRRDATATRANSWDATA
Normal case1da(pc+2i)N cycle 
 2pc+3i-N cycleRd
   (pc+3i)  
Scaled offset1pc+3i(pc+2i)I cycle 
 2da-N cycle 
 3pc+3i-N cycleRd
   pc+3i  
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