9.26. Coprocessor absent

If no coprocessor is able to process a coprocessor instruction, the instruction is treated as an undefined instruction. This enables software to emulate coprocessor instructions when no hardware coprocessor is present.

Note

By default, CHSD and CHSE must be driven to ABSENT unless the coprocessor instruction is being handled by a coprocessor. Coprocessor operations are only available in ARM state.

The cycle timings for coprocessor absent instructions are shown in Table 9.33, where:

P

Indicates the signal CPPASS.

LC

Indicates the signal CPLATECANCEL.

Table 9.33. Cycle timings for coprocessor absent

CycleADDRRDATATRANSCPINSTRP LC CHSDCHSE
Coprocessor absent in decode  (pc)    
 1pc+3i(pc+2i)I cycle(pc+i) 0ABSENT 
 2pc+3i-I cycle(pc+2i)10 -
 30x4-N cycle(pc+2i)10 -
 40x8(0x4)S cycle(pc+2i)01 -
 50xC(0x8)S cycle(0x4)00 -
   (0xC) (0x8)    
Coprocessor absent in execute   (pc)    
 1pc+3i(pc+2i)I cycle(pc+i)00WAIT 
 .pc+3i-I cycle(pc+2i)10 WAIT
 n+1pc+3i-I cycle(pc+2i)10 ABSENT
 n+2pc+3i-I cycle(pc+2i)10 -
 n+30x4-N cycle(pc+2i)10 -
 n+40x8(0x4)S cycle(pc+2i)01 -
 n+50xc(0x8)S cycle(0x4)00 -
   (0xC) (0x8)    

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