9.23. Coprocessor register transfer (from ARM)

The move to coprocessor (MCR) operation transfers a specified ARM register to a coprocessor register.

An interrupt can cause the ARM7EJ-S processor to abandon a busy-waiting coprocessor instruction (see Busy-waiting and interrupts).

Note

Coprocessor operations are only available in ARM state.

The MCR instruction cycle timings are shown in Table 9.30, where:

P

Indicates the signal CPPASS.

LC

Indicates the signal CPLATECANCEL.

Table 9.30. Cycle timings for MCR

Cycle ADDRRDATATRANSCPINSTRCPDOUTP LC CHSDCHSE
Ready    (pc)     
 1pc+3i(pc+2i)I cycle(pc+i) 00LAST 
 2pc+3i-S cycle(pc+2i) 10 -
   (pc+3i) (pc+2i)     
     (pc+3i)Rd    
Not ready   (pc)     
 1pc+3i(pc+2i)I cycle(pc+i) 00 WAIT
 .pc+3i-I cycle(pc+2i) 10 WAIT
 n+1pc+3i-I cycle(pc+2i) 10 LAST
 n+2pc+3i-S cycle(pc+2i) 10 -
   (pc+3i) (pc+2i)     
     (pc+3i)Rd    
Copyright ©  2001 ARM Limited. All rights reserved.ARM DDI 0214B
Non-Confidential