9.25. Double coprocessor register transfer (from ARM)

The move double to coprocessor (MCRR) operation transfers two specified ARM registers to a coprocessor.

An interrupt can cause the ARM7EJ-S processor to abandon a busy-waiting coprocessor instruction (see Busy-waiting and interrupts).

Note

Coprocessor operations are only available in ARM state.

The MCRR instruction cycle timings are shown in Table 9.32, where:

P

Indicates the signal CPPASS.

LC

Indicates the signal CPLATECANCEL.

Table 9.32. Cycle timings for MCRR

CycleADDRRDATATRANSCPINSTRCPDOUTPLCCHSDCHSE
ready    (pc)     
 1pc+3i(pc+2i)I cycle(pc+i) 00GO 
 2pc+3i-I cycle(pc+2i) 10 LAST
 3pc+3i-S cycle(pc+2i) 10 -
   (pc+3i) (pc+2i)Rd    
     (pc+3i)Rn    
not ready    (pc)     
 1pc+3i(pc+2i)I cycle(pc+i) 00WAIT 
 .pc+3i-I cycle(pc+2i) 10 WAIT
 n+1pc+3i-I cycle(pc+2i) 10 GO
 n+2pc+3i-I cycle(pc+2i) 10 LAST
 n+3pc+3i-S cycle(pc+2i) 10 -
   (pc+3i) (pc+2i)Rd    
     (pc+3i)Rn    
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