9.5. Thumb Branch, Link, and Exchange immediate

A Thumb Branch, Link, and Exchange immediate (BLX <immediate>) operation is similar to a Thumb BL operation. It comprises two consecutive Thumb instructions, and takes four cycles:

  1. The first instruction acts as a simple data operation. It takes a single cycle to add the PC to the upper part of the offset and store the result in r14. If the previous instruction requested a data memory access, the data is transferred in this cycle.

  2. The second instruction acts similarly to the ARM BLX instruction:

    1. During the first cycle, the ARM7EJ-S processor calculates the final branch target address while performing a prefetch from the current PC.

    2. During the second cycle, the ARM7EJ-S processor performs a fetch from the branch destination, using the new instruction width, dependent on the state that has been selected. The return address to be stored in r14 is calculated.

    3. During the third cycle, the ARM7EJ-S processor performs a fetch from the destination + 4, refilling the instruction pipeline.

Table 9.6 shows the cycle timings of the complete operation.

Table 9.6. Cycle timings for Thumb Branch, Link, and Exchange

CycleADDRRDATATRANSCPTBIT
1pc+3i(pc+2i)S cyclet
2pc'(pc+3i)N cyclet'
3pc'+i(pc')S cyclet'
4pc'+2i(pc'+i)S cyclet'
  (pc'+2i)  
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