9.13. Load multiple registers

A load multiple (LDM) instruction takes several cycles to execute, depending on the number of registers transferred and whether the PC is in the list of registers transferred:

  1. During the first cycle, the ARM7EJ-S processor calculates the address of the first word to be transferred, while performing an instruction prefetch.

  2. During the second and subsequent cycles, the ARM7EJ-S processor reads the data requested in the previous cycle and calculates the address of the next word to be transferred. The new value for the base register is calculated.

When a Data Abort occurs, the instruction continues to completion. The ARM7EJ-S processor prevents all register writing after the abort. The ARM7EJ-S processor restores the modified base pointer (which the load activity before the abort occurred might have overwritten).

When the PC is in the list of registers to be loaded, the ARM7EJ-S processor invalidates the current contents of the instruction pipeline. The PC is always the last register to be loaded, so an abort at any point prevents the PC from being overwritten.

Note

LDM with destination = PC cannot be executed in Thumb state. However, POP{Rlist, PC} equates to an LDM with destination = PC.

Table 9.22 shows the LDM cycle timings.

Table 9.22. Cycle timings for LDM

CycleADDRRDATATRANS
1 register (not PC)   
 1da(pc+2i)N cycle
 2pc+3i(da)N cycle
   (pc+3i) 
n registers (n > 1) (not PC)  
 1da(pc+2i)N cycle
 2da++(da)S cycle
 .da++(da++)S cycle
 nda++(da++)S cycle
 n+1pc+3i(da++)N cycle
   (pc+3i) 
1 register, dest=pc   
 1da(pc+2i)N cycle
 2pc+3i(da)I cycle
 3pc'-N cycle
 4pc'+i(pc')S cycle
 5pc'+2i(pc'+i)S cycle
   (pc'+2i) 
     
n registers (n >1) (incl pc)  
 1da(pc+2i)N cycle
 2da++(da)S cycle
 .da++(da++)S cycle
 nda++(da++)S cycle
 n + 1pc+3i(da++)I cycle
 n + 2pc'-N cycle
 n + 3pc'+i(pc')S cycle
 n + 4pc'+2i(pc'+i)S cycle
   (pc'+2i) 
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