10.7. JTAG interface

JTAG interface timing parameters are shown in Figure 10.6. The timing parameters used in Figure 10.6 are shown in Table 10.6.

Figure 10.6. JTAG interface timing

Table 10.6. JTAG interface timing parameters

SymbolParameterMinMax

Tihntrst

DBGnTRST input hold from rising CLK

15%

-

Tihtapid

TAPID input hold time from rising CLK

15%

-

Tihtcken

DBGTCKEN input hold from rising CLK

15%

-

Tihtdi

DBGTDI input hold from rising CLK

15%

-

Tihtms

DBGTMS input hold from rising CLK

15%

-

Tisntrst

DBGnTRST input setup to rising CLK

25%

-

Tistapid

TAPID input setup to rising CLK

25%

-

Tistcken

DBGTCKEN input setup to rising CLK

35%

-

Tistdi

DBGTDI input setup to rising CLK

35%

-

Tistms

DBGTMS input setup to rising CLK

35%

-

Tohdbgsm

Debug state hold from rising CLK

0%

-

Tohsdin

DBGSDIN hold from rising CLK

0%

-

Tohtdo

DBGTDO hold from rising CLK

0%

-

Tohtdoen

DBGnTDOEN hold from rising CLK

0%

-

Tovdbgsm

Rising CLK to debug state valid

-

50%

Tovsdin

Rising CLK to DBGSDIN valid

-

50%

Tovtdo

Rising CLK to DBGTDO valid

-

50%

Tovtdoen

Rising CLK to DBGnTDOEN valid

-

60%

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