ARM7EJ-S Technical Reference Manual 10.2. Memory interface

ARM7EJ-S Technical Reference Manual

(Rev 1)

Home > AC Parameters > Memory interface

10.2. Memory interface

Memory interface timing parameters are shown in Figure 10.1. The timing parameters used in Figure 10.1 are shown in Table 10.1.

Figure 10.1. Memory interface timing

Table 10.1. Memory interface timing parameters

Symbol	Parameter	Min	Max
T_ihabort	ABORT input hold from rising CLK	15%	-
T_ihclken	CLKEN input hold from rising CLK	15%	-
T_ihrdata	RDATA input hold from rising CLK	15%	-
T_isabort	ABORT input setup to rising CLK	25%	-
T_isclken	CLKEN input setup to rising CLK	40%	-
T_isrdata	RDATA input setup to rising CLK	25%	-
T_ohaddr	ADDR hold time from rising CLK	0%	-
T_ohctl	Control hold time from rising CLK	0%	-
T_ohtrans	Transaction type hold time from rising CLK	0%	-
T_ohwdata	WDATA hold time from rising CLK	0%	-
T_ovaddr	Rising CLK to ADDR valid	-	65%
T_ovctl	Rising CLK to control valid	-	65%
T_ovtrans	Rising CLK to transaction type valid	-	65%
T_ovwdata	Rising CLK to WDATA valid	-	60%

Copyright © 2001 ARM Limited. All rights reserved.	ARM DDI 0214B
Non-Confidential
PDF version

Home > AC Parameters > Memory interface