10.2. Memory interface

Memory interface timing parameters are shown in Figure 10.1. The timing parameters used in Figure 10.1 are shown in Table 10.1.

Figure 10.1. Memory interface timing

Table 10.1. Memory interface timing parameters

Symbol

Parameter

Min

Max

Tihabort

ABORT input hold from rising CLK

15%

-

Tihclken

CLKEN input hold from rising CLK

15%

-

Tihrdata

RDATA input hold from rising CLK

15%

-

Tisabort

ABORT input setup to rising CLK

25%

-

Tisclken

CLKEN input setup to rising CLK

40%

-

Tisrdata

RDATA input setup to rising CLK

25%

-

Tohaddr

ADDR hold time from rising CLK

0%

-

Tohctl

Control hold time from rising CLK

0%

-

Tohtrans

Transaction type hold time from rising CLK

0%

-

Tohwdata

WDATA hold time from rising CLK

0%

-

Tovaddr

Rising CLK to ADDR valid

-

65%

Tovctl

Rising CLK to control valid

-

65%

Tovtrans

Rising CLK to transaction type valid

-

65%

Tovwdata

Rising CLK to WDATA valid

-

60%

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