10.3. Coprocessor interface

Coprocessor interface timing parameters are shown in Figure 10.2. The timing parameters used in Figure 10.2 are shown in Table 10.2.

Figure 10.2. Coprocessor interface timing

Table 10.2. Coprocessor interface timing parameters

Symbol

Parameter

MinMax

Tihchsd

CHSD input hold from rising CLK

15%

-

Tihchse

CHSE input hold from rising CLK

15%

-

Tihcpdin

CPDIN input hold from rising CLK

15%

-

Tischsd

CHSD input setup to rising CLK

35%

-

Tischse

CHSE input setup to rising CLK

35%

-

Tiscpdin

CPDIN input setup to rising CLK

35%-

Tohcpcontrol

CPnMREQ, CPnTRANS, CPTBIT, and CPJBIT hold from rising CLK0%-

Tohcpdout

CPDOUT hold time from CLK rising

0%-

Tohcpinstr

CPINSTR hold time from CLK rising

0%-

Tohlate

CPLATECANCEL hold from CLK rising

0%

-

Tohpass

CPPASS hold time from CLK rising

0%

-

Tovcpcontrol

Rising CLK to CPnMREQ, CPnTRANS, CPTBIT, and CPJBIT valid

-35%

Tovcpdout

Rising CLK to CPDOUT valid

-35%

Tovcpinstr

Rising CLK to CPINSTR valid

-35%

Tovlate

Rising CLK to CPLATECANCEL valid

-

35%

Tovpass

Rising CLK to CPPASS valid

-

35%

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