1.4.2. Extended ARM instruction set summary

The extended ARM instruction set summary is given in Table 1.2.

Table 1.2. ARM instruction set summary

MoveMoveMOV{cond}{S} Rd, <Oprnd2>
 Move NOTMVN{cond}{S} Rd, <Oprnd2>
 Move SPSR to registerMRS{cond} Rd, SPSR
 Move CPSR to registerMRS{cond} Rd, CPSR
 Move register to SPSRMSR{cond} SPSR{field}, Rm
 Move register to CPSRMSR{cond} CPSR{field}, Rm
 Move immediate to SPSR flagsMSR{cond} SPSR_flg, #32bit_Imm
 Move immediate to CPSR flagsMSR{cond} CPSR_flg, #32bit_Imm
ArithmeticAddADD{cond}{S} Rd, Rn, <Oprnd2>
 Add with carryADC{cond}{S} Rd, Rn, <Oprnd2>
 SubtractSUB{cond}{S} Rd, Rn, <Oprnd2>
 Subtract with carrySBC{cond}{S} Rd, Rn, <Oprnd2>
 Reverse subtractRSB{cond}{S} Rd, Rn, <Oprnd2>
 Reverse subtract with carryRSC{cond}{S} Rd, Rn, <Oprnd2>
 MultiplyMUL{cond}{S} Rd, Rm, Rs
 Multiply accumulateMLA{cond}{S} Rd, Rm, Rs, Rn
 Multiply unsigned longUMULL{cond}{S} RdLo, RdHi, Rm, Rs
 Multiply unsigned accumulate longUMLAL{cond}{S} RdLo, RdHi, Rm, Rs
 Multiply signed longSMULL{cond}{S} RdLo, RdHi, Rm, Rs
 Multiply signed accumulate longSMLAL{cond}{S} RdLo, RdHi, Rm, Rs
 CompareCMP{cond} Rd, <Oprnd2>
 Compare negativeCMN{cond} Rd, <Oprnd2>
 Saturating addQADD{cond} Rd, Rn, Rs
 Saturating add with doubleQDADD{cond} Rd, Rn, Rs
 Saturating subtractQSUB{cond} Rd, Rn, Rs
 Saturating subtract with doubleQDSUB{cond} Rd, Rn, Rs
 Multiply 16x16SMULxy{cond} Rd, Rm, Rs
 Multiply accumulate 16x16+32SMULAxy{cond} Rd, Rm, Rs, Rn
 Multiply 32x16SMULWx{cond} Rd, Rm, Rs
 Multiply accumulate 32x16+32SMLAWx{cond} Rd, Rm, Rs, Rn
 Multiply signed accumulate long 16x16+64SMLALx{cond} RdLo, RdHi, Rm, Rs
 Count leading zerosCLZ{cond} Rd, Rm
LogicalTestTST{cond} Rn, <Oprnd2>
 Test equivalenceTEQ{cond} Rn, <Oprnd2>
 ANDAND{cond}{S} Rd, Rn, <Oprnd2>
 XOREOR{cond}{S} Rd, Rn, <Oprnd2>
 ORORR{cond}{S} Rd, Rn, <Oprnd2>
 Bit clearBIC{cond}{S} Rd, Rn, <Oprnd2>
BranchBranchB{cond} label
 Branch with linkBL{cond} label
Branch and exchangeBX{cond} Rn
Branch, link and exchangeBLX{cond} label
Branch, link and exchangeBLX{cond} Rn
Branch and exchange to Jazelle stateBXJ{cond} Rm
LoadWordLDR{cond} Rd, <a_mode2>
 Word with User mode privilegeLDR{cond}T Rd, <a_mode2P>
 ByteLDR{cond}B Rd, <a_mode2>
 Byte with User mode privilegeLDR{cond}BT Rd, <a_mode2P>
 Byte signedLDR{cond}SB Rd, <a_mode3>
 HalfwordLDR{cond}H Rd, <a_mode3>
 Halfword signedLDR{cond}SH Rd, <a_mode3>
 Multiple block data operationsLDM{cond}<a_mode4L> Rd{!}, <reglist>
  • Increment before

LDM{cond}IB Rd{!}, <reglist>{^}
  • Increment after

LDM{cond}IA Rd{!}, <reglist>{^}
  • Decrement before

LDM{cond}DB Rd{!}, <reglist>{^}
  • Decrement after

LDM{cond}DA Rd{!}, <reglist>{^}
  • Stack operations and restore CPSR

LDM{cond}<a_mode4L> Rd{!}, <reglist+PC>^
  • User registers

LDM{cond}<a_mode4L> Rd{!}, <reglist>^
  • Load double

LDR{cond}D Rd, <a_mode3>
StoreWordSTR{cond} Rd, <a_mode2>
 Word with User mode privilegeSTR{cond}T Rd, <a_mode2P>
 ByteSTR{cond}B Rd, <a_mode2>
 Byte with User mode privilegeSTR{cond}BT Rd, <a_mode2P>
 HalfwordSTR{cond}H Rd, <a_mode3>
 Multiple block data operationsSTM{cond}<a_mode4S> Rd{!}, <reglist>
  • Increment before

STM{cond}IB Rd{!}, <reglist>{^}
  • Increment after

STM{cond}IA Rd{!}, <reglist>{^}
  • Decrement before

STM{cond}DB Rd{!}, <reglist>{^}
  • Decrement after

STM{cond}DA Rd{!}, <reglist>{^}
  • User registers

STM{cond}<a_mode4S> Rd{!}, <reglist>^
  • Store double

STR{cond}D Rd, <a_mode3>
Soft preloadMemory may prepare to load from addressPLD <a_mode2>
SwapWordSWP{cond} Rd, Rm, [Rn]
 ByteSWP{cond}B Rd, Rm, [Rn]
CoprocessorsData operationsCDP{cond} p<cpnum>, <op1>, CRd, CRn, CRm, <op2>
Move to ARM reg from coprocessorMRC{cond} p<cpnum>, <op1>, Rd, CRn, CRm, <op2>
Move to coprocessor from ARM registerMCR{cond} p<cpnum>, <op1>, Rd, CRn, CRm, <op2>
Move double to ARM register from coprocessorMRRC{cond} p<cpnum>, <op1>, Rd, Rn, CRm
Move double to coprocessor from ARM registerMCRR{cond} p<cpnum>, <op1>, Rd, Rn, CRm
LoadLDC{cond} p<cpnum>, CRd, <a_mode5>
StoreSTC{cond} p<cpnum>, CRd, <a_mode5>
Software interrupt-SWI{cond} 24bit_Imm
Software breakpoint-BKPT<immediate>

Addressing modes

The addressing modes enable all load and store addresses to be determined from register contents and instruction fields only. The five addressing modes used by the ARM7EJ-S processor are:

Mode 1

Shifter operands for data processing instructions.

Mode 2

Load and store word or unsigned byte.

Mode 3

Load and store halfword or load signed byte.

Mode 4

Load and store multiple.

Mode 5

Load and store coprocessor.

The addressing modes are shown with their types and mnemonics in Table 1.3.

Table 1.3. Addressing modes

Addressing modeType or addressing modeMnemonic or stack type
Mode 2 <a_mode2>Immediate offset[Rn, #+/-12bit_Offset]
 Register offset[Rn, +/-Rm]
 Scaled register offset[Rn, +/-Rm, LSL #5bit_shift_imm]
  [Rn, +/-Rm, LSR #5bit_shift_imm]
  [Rn, +/-Rm, ASR #5bit_shift_imm]
  [Rn, +/-Rm, ROR #5bit_shift_imm]
  [Rn, +/-Rm, RRX]
 Pre-indexed offset-
 Immediate[Rn, #+/-12bit_Offset]!
 Register[Rn, +/-Rm]!
 Scaled register[Rn, +/-Rm, LSL #5bit_shift_imm]!
  [Rn, +/-Rm, LSR #5bit_shift_imm]!
  [Rn, +/-Rm, ASR #5bit_shift_imm]!
  [Rn, +/-Rm, ROR #5bit_shift_imm]!
  [Rn, +/-Rm, RRX]!
 Post-indexed offset-
 Immediate [Rn], #+/-12bit_Offset
 Register [Rn], +/-Rm
 Scaled register [Rn], +/-Rm, LSL #5bit_shift_imm
  [Rn], +/-Rm, LSR #5bit_shift_imm
  [Rn], +/-Rm, ASR #5bit_shift_imm
  [Rn], +/-Rm, ROR #5bit_shift_imm
  [Rn], +/-Rm, RRX
Mode 2 (privileged <a_mode2P>)Immediate offset[Rn, #+/-12bit_Offset]
 Register offset[Rn, +/-Rm]
 Scaled register offset[Rn, +/-Rm, LSL #5bit_shift_imm]
  [Rn, +/-Rm, LSR #5bit_shift_imm]
  [Rn, +/-Rm, ASR #5bit_shift_imm]
  [Rn, +/-Rm, ROR #5bit_shift_imm]
  [Rn, +/-Rm, RRX]
 Post-indexed offset-
 Immediate [Rn], #+/-12bit_Offset
 Register [Rn], +/-Rm
 Scaled register [Rn], +/-Rm, LSL #5bit_shift_imm
  [Rn], +/-Rm, LSR #5bit_shift_imm
  [Rn], +/-Rm, ASR #5bit_shift_imm
  [Rn], +/-Rm, ROR #5bit_shift_imm
  [Rn], +/-Rm, RRX
Mode 3 <a_mode3>Immediate offset[Rn, #+/-8bit_Offset]
 Pre-indexed [Rn, #+/-8bit_Offset]!
 Post-indexed [Rn], #+/-8bit_Offset
 Register offset[Rn, +/-Rm]
 Pre-indexed [Rn, +/-Rm]!
 Post-indexed [Rn], +/-Rm
Mode 4 (load) <a_mode4L>IA Increment afterFD Full descending
 IB Increment beforeED Empty descending
 DA Decrement afterFA Full ascending
 DB Decrement beforeEA Empty ascending
Mode 4 (store) <a_mode4S>IA Increment afterEA Empty ascending
 IB Increment beforeFA Full ascending
 DA Decrement afterED Empty descending
 DB Decrement beforeFD Full descending
Mode 5 <a_mode5>)Immediate offset[Rn, #+/-(8bit_Offset*4)]
  Pre-indexed[Rn, #+/-(8bit_Offset*4)]!
  Post-indexed[Rn], #+/-(8bit_Offset*4)

Operand 2

An operand is the part of the instruction that references data or a peripheral device. Operand2 is shown in Table 1.4.

Table 1.4. Operand2

Operand 2 <oprnd2>Immediate value#32bit_Imm
 Logical shift leftRm LSL #5bit_Imm
 Logical shift rightRm LSR #5bit_Imm
 Arithmetic shift rightRm ASR #5bit_Imm
 Rotate rightRm ROR #5bit_Imm
 Logical shift leftRm LSL Rs
 Logical shift rightRm LSR Rs
 Arithmetic shift rightRm ASR Rs
 Rotate rightRm ROR Rs
 Rotate right extendedRm RRX


Fields are shown in Table 1.5.

Table 1.5. Fields

Field {field}_cControl field mask bit (bit 0)3
 _xExtension field mask bit (bit 1)0
 _sStatus field mask bit (bit 2)1
 _fFlags field mask bit (bit 3)2

Condition fields

Condition fields are shown in Table 1.6.

Table 1.6. Condition fields

Field typeSuffixDescriptionCondition

Condition {cond}


Z set

 NENot equal

Z clear

 HS/CSUnsigned higher or same

C set

 LO/CCUnsigned lower

C clear


N set

 PLPositive or zero

N clear


V set

 VCNo overflow

V clear

 HIUnsigned higher

C set, Z clear

 LSUnsigned lower or same

C clear, Z set

 GEGreater or equal

N and V set, or N and V clear

 LTLess than

N set and V clear, or N clear and V set

 GTGreater than

Z clear and (N and V set, or N and V clear)

 LELess than or equal

Z set or (N set and V clear) or (N clear and V set)


Flag ignored

Copyright ©  2001 ARM Limited. All rights reserved.ARM DDI 0214B