9.1. About instruction cycle timings

The pipelined architecture of the ARM7EJ-S processor overlaps the execution of several instructions in different pipeline stages. The tables in this chapter show the number of cycles required by an instruction when it has reached the Execute stage of the pipeline.

The instruction cycle count is the number of cycles for which an instruction occupies the Execute stage of the pipeline. The other pipeline stages (Fetch, Decode, Memory, and Writeback) are only occupied for one cycle by any instruction (in this model, interlock cycles are grouped in with the instruction generating the data that creates the interlock condition, not the instruction dependent on the data).

The request, address, and control signals on the memory interface are pipelined so that they are generated in the cycle before the one to which they apply. They are shown this way in the tables in this chapter.

The instruction address, ADDR[31:0], is incremented for prefetching instructions in most cases. The increment varies with the instruction length:

The letter i is used to indicate the instruction length.


All cycle counts in this chapter assume zero wait-state memory access. In a system where CLKEN is used to add wait states, the cycle counts must be adjusted accordingly.

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