5.4. LDC operation

The number of words transferred is determined by how the coprocessor drives the CHSD[1:0] and CHSE[1:0] buses. In the example LDC cycle timing shown in Figure 5.1, one word of data is transferred.

Figure 5.1. LDC cycle timing


The coprocessor must sample the CPDOUT bus at the end of the coprocessor write stage.

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